@@ -315,7 +315,7 @@ static int uwire_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
315315 int div2 ;
316316 int status ;
317317
318- uwire = spi_master_get_devdata (spi -> master );
318+ uwire = spi_controller_get_devdata (spi -> controller );
319319
320320 /* mode 0..3, clock inverted separately;
321321 * standard nCS signaling;
@@ -448,25 +448,25 @@ static void uwire_off(struct uwire_spi *uwire)
448448{
449449 uwire_write_reg (UWIRE_SR3 , 0 );
450450 clk_disable_unprepare (uwire -> ck );
451- spi_master_put (uwire -> bitbang .master );
451+ spi_controller_put (uwire -> bitbang .master );
452452}
453453
454454static int uwire_probe (struct platform_device * pdev )
455455{
456- struct spi_master * master ;
456+ struct spi_controller * host ;
457457 struct uwire_spi * uwire ;
458458 int status ;
459459
460- master = spi_alloc_master (& pdev -> dev , sizeof (* uwire ));
461- if (!master )
460+ host = spi_alloc_host (& pdev -> dev , sizeof (* uwire ));
461+ if (!host )
462462 return - ENODEV ;
463463
464- uwire = spi_master_get_devdata ( master );
464+ uwire = spi_controller_get_devdata ( host );
465465
466466 uwire_base = devm_ioremap (& pdev -> dev , UWIRE_BASE_PHYS , UWIRE_IO_SIZE );
467467 if (!uwire_base ) {
468468 dev_dbg (& pdev -> dev , "can't ioremap UWIRE\n" );
469- spi_master_put ( master );
469+ spi_controller_put ( host );
470470 return - ENOMEM ;
471471 }
472472
@@ -476,24 +476,24 @@ static int uwire_probe(struct platform_device *pdev)
476476 if (IS_ERR (uwire -> ck )) {
477477 status = PTR_ERR (uwire -> ck );
478478 dev_dbg (& pdev -> dev , "no functional clock?\n" );
479- spi_master_put ( master );
479+ spi_controller_put ( host );
480480 return status ;
481481 }
482482 clk_prepare_enable (uwire -> ck );
483483
484484 uwire_write_reg (UWIRE_SR3 , 1 );
485485
486486 /* the spi->mode bits understood by this driver: */
487- master -> mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH ;
488- master -> bits_per_word_mask = SPI_BPW_RANGE_MASK (1 , 16 );
489- master -> flags = SPI_CONTROLLER_HALF_DUPLEX ;
487+ host -> mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH ;
488+ host -> bits_per_word_mask = SPI_BPW_RANGE_MASK (1 , 16 );
489+ host -> flags = SPI_CONTROLLER_HALF_DUPLEX ;
490490
491- master -> bus_num = 2 ; /* "official" */
492- master -> num_chipselect = 4 ;
493- master -> setup = uwire_setup ;
494- master -> cleanup = uwire_cleanup ;
491+ host -> bus_num = 2 ; /* "official" */
492+ host -> num_chipselect = 4 ;
493+ host -> setup = uwire_setup ;
494+ host -> cleanup = uwire_cleanup ;
495495
496- uwire -> bitbang .master = master ;
496+ uwire -> bitbang .master = host ;
497497 uwire -> bitbang .chipselect = uwire_chipselect ;
498498 uwire -> bitbang .setup_transfer = uwire_setup_transfer ;
499499 uwire -> bitbang .txrx_bufs = uwire_txrx ;
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