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Merge tag 'riscv-sophgo-dt-for-v6.10' of https://github.com/sophgo/linux into soc/dt
RISC-V Devicetrees for v6.10 Sophgo: Added sdhci support for cv18xx/duo. Added clock support for cv18xx. Added clock for uart/sdhci. Added spi support for cv18xx. Added i2c support for cv18xx. Added reserved memory node for cv1800b/duo. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * tag 'riscv-sophgo-dt-for-v6.10' of https://github.com/sophgo/linux: riscv: dts: sophgo: add reserved memory node for CV1800B riscv: dts: sophgo: use real clock for sdhci riscv: dts: sophgo: cv18xx: Add i2c devices riscv: dts: sophgo: cv18xx: Add spi devices riscv: dts: sophgo: add uart clock for Sophgo CV1800 series SoC riscv: dts: sophgo: add clock generator for Sophgo CV1800 series SoC riscv: dts: sophgo: add sdcard support for milkv duo Link: https://lore.kernel.org/r/MA0P287MB2822CA2DE757787D6EA3B1F8FE192@MA0P287MB2822.INDP287.PROD.OUTLOOK.COM Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2 parents 5c04a5b + 1eba0b6 commit 0ea32f5

4 files changed

Lines changed: 157 additions & 8 deletions

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‎arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts‎

Lines changed: 17 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -23,16 +23,30 @@
2323
stdout-path = "serial0:115200n8";
2424
};
2525

26-
memory@80000000 {
27-
device_type = "memory";
28-
reg = <0x80000000 0x3f40000>;
26+
reserved-memory {
27+
#address-cells = <1>;
28+
#size-cells = <1>;
29+
ranges;
30+
31+
coprocessor_rtos: region@83f40000 {
32+
reg = <0x83f40000 0xc0000>;
33+
no-map;
34+
};
2935
};
3036
};
3137

3238
&osc {
3339
clock-frequency = <25000000>;
3440
};
3541

42+
&sdhci0 {
43+
status = "okay";
44+
bus-width = <4>;
45+
no-1-8-v;
46+
no-mmc;
47+
no-sdio;
48+
};
49+
3650
&uart0 {
3751
status = "okay";
3852
};

‎arch/riscv/boot/dts/sophgo/cv1800b.dtsi‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,11 @@
77

88
/ {
99
compatible = "sophgo,cv1800b";
10+
11+
memory@80000000 {
12+
device_type = "memory";
13+
reg = <0x80000000 0x4000000>;
14+
};
1015
};
1116

1217
&plic {
@@ -16,3 +21,7 @@
1621
&clint {
1722
compatible = "sophgo,cv1800b-clint", "thead,c900-clint";
1823
};
24+
25+
&clk {
26+
compatible = "sophgo,cv1800-clk";
27+
};

‎arch/riscv/boot/dts/sophgo/cv1812h.dtsi‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -22,3 +22,7 @@
2222
&clint {
2323
compatible = "sophgo,cv1812h-clint", "thead,c900-clint";
2424
};
25+
26+
&clk {
27+
compatible = "sophgo,cv1810-clk";
28+
};

‎arch/riscv/boot/dts/sophgo/cv18xx.dtsi‎

Lines changed: 127 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -4,6 +4,8 @@
44
* Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
55
*/
66

7+
#include <dt-bindings/clock/sophgo,cv1800.h>
8+
#include <dt-bindings/gpio/gpio.h>
79
#include <dt-bindings/interrupt-controller/irq.h>
810

911
/ {
@@ -53,6 +55,12 @@
5355
dma-noncoherent;
5456
ranges;
5557

58+
clk: clock-controller@3002000 {
59+
reg = <0x03002000 0x1000>;
60+
clocks = <&osc>;
61+
#clock-cells = <1>;
62+
};
63+
5664
gpio0: gpio@3020000 {
5765
compatible = "snps,dw-apb-gpio";
5866
reg = <0x3020000 0x1000>;
@@ -125,11 +133,67 @@
125133
};
126134
};
127135

136+
i2c0: i2c@4000000 {
137+
compatible = "snps,designware-i2c";
138+
reg = <0x04000000 0x10000>;
139+
#address-cells = <1>;
140+
#size-cells = <0>;
141+
clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C0>;
142+
clock-names = "ref", "pclk";
143+
interrupts = <49 IRQ_TYPE_LEVEL_HIGH>;
144+
status = "disabled";
145+
};
146+
147+
i2c1: i2c@4010000 {
148+
compatible = "snps,designware-i2c";
149+
reg = <0x04010000 0x10000>;
150+
#address-cells = <1>;
151+
#size-cells = <0>;
152+
clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C1>;
153+
clock-names = "ref", "pclk";
154+
interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
155+
status = "disabled";
156+
};
157+
158+
i2c2: i2c@4020000 {
159+
compatible = "snps,designware-i2c";
160+
reg = <0x04020000 0x10000>;
161+
#address-cells = <1>;
162+
#size-cells = <0>;
163+
clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C2>;
164+
clock-names = "ref", "pclk";
165+
interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
166+
status = "disabled";
167+
};
168+
169+
i2c3: i2c@4030000 {
170+
compatible = "snps,designware-i2c";
171+
reg = <0x04030000 0x10000>;
172+
#address-cells = <1>;
173+
#size-cells = <0>;
174+
clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C3>;
175+
clock-names = "ref", "pclk";
176+
interrupts = <52 IRQ_TYPE_LEVEL_HIGH>;
177+
status = "disabled";
178+
};
179+
180+
i2c4: i2c@4040000 {
181+
compatible = "snps,designware-i2c";
182+
reg = <0x04040000 0x10000>;
183+
#address-cells = <1>;
184+
#size-cells = <0>;
185+
clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C4>;
186+
clock-names = "ref", "pclk";
187+
interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
188+
status = "disabled";
189+
};
190+
128191
uart0: serial@4140000 {
129192
compatible = "snps,dw-apb-uart";
130193
reg = <0x04140000 0x100>;
131194
interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
132-
clocks = <&osc>;
195+
clocks = <&clk CLK_UART0>, <&clk CLK_APB_UART0>;
196+
clock-names = "baudclk", "apb_pclk";
133197
reg-shift = <2>;
134198
reg-io-width = <4>;
135199
status = "disabled";
@@ -139,7 +203,8 @@
139203
compatible = "snps,dw-apb-uart";
140204
reg = <0x04150000 0x100>;
141205
interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
142-
clocks = <&osc>;
206+
clocks = <&clk CLK_UART1>, <&clk CLK_APB_UART1>;
207+
clock-names = "baudclk", "apb_pclk";
143208
reg-shift = <2>;
144209
reg-io-width = <4>;
145210
status = "disabled";
@@ -149,7 +214,8 @@
149214
compatible = "snps,dw-apb-uart";
150215
reg = <0x04160000 0x100>;
151216
interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
152-
clocks = <&osc>;
217+
clocks = <&clk CLK_UART2>, <&clk CLK_APB_UART2>;
218+
clock-names = "baudclk", "apb_pclk";
153219
reg-shift = <2>;
154220
reg-io-width = <4>;
155221
status = "disabled";
@@ -159,22 +225,78 @@
159225
compatible = "snps,dw-apb-uart";
160226
reg = <0x04170000 0x100>;
161227
interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
162-
clocks = <&osc>;
228+
clocks = <&clk CLK_UART3>, <&clk CLK_APB_UART3>;
229+
clock-names = "baudclk", "apb_pclk";
163230
reg-shift = <2>;
164231
reg-io-width = <4>;
165232
status = "disabled";
166233
};
167234

235+
spi0: spi@4180000 {
236+
compatible = "snps,dw-apb-ssi";
237+
reg = <0x04180000 0x10000>;
238+
#address-cells = <1>;
239+
#size-cells = <0>;
240+
clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI0>;
241+
clock-names = "ssi_clk", "pclk";
242+
interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
243+
status = "disabled";
244+
};
245+
246+
spi1: spi@4190000 {
247+
compatible = "snps,dw-apb-ssi";
248+
reg = <0x04190000 0x10000>;
249+
#address-cells = <1>;
250+
#size-cells = <0>;
251+
clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI1>;
252+
clock-names = "ssi_clk", "pclk";
253+
interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
254+
status = "disabled";
255+
};
256+
257+
spi2: spi@41a0000 {
258+
compatible = "snps,dw-apb-ssi";
259+
reg = <0x041a0000 0x10000>;
260+
#address-cells = <1>;
261+
#size-cells = <0>;
262+
clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI2>;
263+
clock-names = "ssi_clk", "pclk";
264+
interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
265+
status = "disabled";
266+
};
267+
268+
spi3: spi@41b0000 {
269+
compatible = "snps,dw-apb-ssi";
270+
reg = <0x041b0000 0x10000>;
271+
#address-cells = <1>;
272+
#size-cells = <0>;
273+
clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI3>;
274+
clock-names = "ssi_clk", "pclk";
275+
interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;
276+
status = "disabled";
277+
};
278+
168279
uart4: serial@41c0000 {
169280
compatible = "snps,dw-apb-uart";
170281
reg = <0x041c0000 0x100>;
171282
interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
172-
clocks = <&osc>;
283+
clocks = <&clk CLK_UART4>, <&clk CLK_APB_UART4>;
284+
clock-names = "baudclk", "apb_pclk";
173285
reg-shift = <2>;
174286
reg-io-width = <4>;
175287
status = "disabled";
176288
};
177289

290+
sdhci0: mmc@4310000 {
291+
compatible = "sophgo,cv1800b-dwcmshc";
292+
reg = <0x4310000 0x1000>;
293+
interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
294+
clocks = <&clk CLK_AXI4_SD0>,
295+
<&clk CLK_SD0>;
296+
clock-names = "core", "bus";
297+
status = "disabled";
298+
};
299+
178300
plic: interrupt-controller@70000000 {
179301
reg = <0x70000000 0x4000000>;
180302
interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;

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