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andredlag-linaro
andred
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mfd: sec-irq: Convert to using REGMAP_IRQ_REG() macros
Use REGMAP_IRQ_REG macro helpers instead of open coding. This makes the code a bit shorter and more obvious. Signed-off-by: André Draszik <andre.draszik@linaro.org> Link: https://lore.kernel.org/r/20250409-s2mpg10-v4-22-d66d5f39b6bf@linaro.org Signed-off-by: Lee Jones <lee@kernel.org>
1 parent 55684cb commit 10008dc

1 file changed

Lines changed: 75 additions & 268 deletions

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‎drivers/mfd/sec-irq.c‎

Lines changed: 75 additions & 268 deletions
Original file line numberDiff line numberDiff line change
@@ -74,212 +74,68 @@ static const struct regmap_irq s2mpg10_irqs[] = {
7474
};
7575

7676
static const struct regmap_irq s2mps11_irqs[] = {
77-
[S2MPS11_IRQ_PWRONF] = {
78-
.reg_offset = 0,
79-
.mask = S2MPS11_IRQ_PWRONF_MASK,
80-
},
81-
[S2MPS11_IRQ_PWRONR] = {
82-
.reg_offset = 0,
83-
.mask = S2MPS11_IRQ_PWRONR_MASK,
84-
},
85-
[S2MPS11_IRQ_JIGONBF] = {
86-
.reg_offset = 0,
87-
.mask = S2MPS11_IRQ_JIGONBF_MASK,
88-
},
89-
[S2MPS11_IRQ_JIGONBR] = {
90-
.reg_offset = 0,
91-
.mask = S2MPS11_IRQ_JIGONBR_MASK,
92-
},
93-
[S2MPS11_IRQ_ACOKBF] = {
94-
.reg_offset = 0,
95-
.mask = S2MPS11_IRQ_ACOKBF_MASK,
96-
},
97-
[S2MPS11_IRQ_ACOKBR] = {
98-
.reg_offset = 0,
99-
.mask = S2MPS11_IRQ_ACOKBR_MASK,
100-
},
101-
[S2MPS11_IRQ_PWRON1S] = {
102-
.reg_offset = 0,
103-
.mask = S2MPS11_IRQ_PWRON1S_MASK,
104-
},
105-
[S2MPS11_IRQ_MRB] = {
106-
.reg_offset = 0,
107-
.mask = S2MPS11_IRQ_MRB_MASK,
108-
},
109-
[S2MPS11_IRQ_RTC60S] = {
110-
.reg_offset = 1,
111-
.mask = S2MPS11_IRQ_RTC60S_MASK,
112-
},
113-
[S2MPS11_IRQ_RTCA1] = {
114-
.reg_offset = 1,
115-
.mask = S2MPS11_IRQ_RTCA1_MASK,
116-
},
117-
[S2MPS11_IRQ_RTCA0] = {
118-
.reg_offset = 1,
119-
.mask = S2MPS11_IRQ_RTCA0_MASK,
120-
},
121-
[S2MPS11_IRQ_SMPL] = {
122-
.reg_offset = 1,
123-
.mask = S2MPS11_IRQ_SMPL_MASK,
124-
},
125-
[S2MPS11_IRQ_RTC1S] = {
126-
.reg_offset = 1,
127-
.mask = S2MPS11_IRQ_RTC1S_MASK,
128-
},
129-
[S2MPS11_IRQ_WTSR] = {
130-
.reg_offset = 1,
131-
.mask = S2MPS11_IRQ_WTSR_MASK,
132-
},
133-
[S2MPS11_IRQ_INT120C] = {
134-
.reg_offset = 2,
135-
.mask = S2MPS11_IRQ_INT120C_MASK,
136-
},
137-
[S2MPS11_IRQ_INT140C] = {
138-
.reg_offset = 2,
139-
.mask = S2MPS11_IRQ_INT140C_MASK,
140-
},
77+
REGMAP_IRQ_REG(S2MPS11_IRQ_PWRONF, 0, S2MPS11_IRQ_PWRONF_MASK),
78+
REGMAP_IRQ_REG(S2MPS11_IRQ_PWRONR, 0, S2MPS11_IRQ_PWRONR_MASK),
79+
REGMAP_IRQ_REG(S2MPS11_IRQ_JIGONBF, 0, S2MPS11_IRQ_JIGONBF_MASK),
80+
REGMAP_IRQ_REG(S2MPS11_IRQ_JIGONBR, 0, S2MPS11_IRQ_JIGONBR_MASK),
81+
REGMAP_IRQ_REG(S2MPS11_IRQ_ACOKBF, 0, S2MPS11_IRQ_ACOKBF_MASK),
82+
REGMAP_IRQ_REG(S2MPS11_IRQ_ACOKBR, 0, S2MPS11_IRQ_ACOKBR_MASK),
83+
REGMAP_IRQ_REG(S2MPS11_IRQ_PWRON1S, 0, S2MPS11_IRQ_PWRON1S_MASK),
84+
REGMAP_IRQ_REG(S2MPS11_IRQ_MRB, 0, S2MPS11_IRQ_MRB_MASK),
85+
86+
REGMAP_IRQ_REG(S2MPS11_IRQ_RTC60S, 1, S2MPS11_IRQ_RTC60S_MASK),
87+
REGMAP_IRQ_REG(S2MPS11_IRQ_RTCA1, 1, S2MPS11_IRQ_RTCA1_MASK),
88+
REGMAP_IRQ_REG(S2MPS11_IRQ_RTCA0, 1, S2MPS11_IRQ_RTCA0_MASK),
89+
REGMAP_IRQ_REG(S2MPS11_IRQ_SMPL, 1, S2MPS11_IRQ_SMPL_MASK),
90+
REGMAP_IRQ_REG(S2MPS11_IRQ_RTC1S, 1, S2MPS11_IRQ_RTC1S_MASK),
91+
REGMAP_IRQ_REG(S2MPS11_IRQ_WTSR, 1, S2MPS11_IRQ_WTSR_MASK),
92+
93+
REGMAP_IRQ_REG(S2MPS11_IRQ_INT120C, 2, S2MPS11_IRQ_INT120C_MASK),
94+
REGMAP_IRQ_REG(S2MPS11_IRQ_INT140C, 2, S2MPS11_IRQ_INT140C_MASK),
14195
};
14296

14397
static const struct regmap_irq s2mps14_irqs[] = {
144-
[S2MPS14_IRQ_PWRONF] = {
145-
.reg_offset = 0,
146-
.mask = S2MPS11_IRQ_PWRONF_MASK,
147-
},
148-
[S2MPS14_IRQ_PWRONR] = {
149-
.reg_offset = 0,
150-
.mask = S2MPS11_IRQ_PWRONR_MASK,
151-
},
152-
[S2MPS14_IRQ_JIGONBF] = {
153-
.reg_offset = 0,
154-
.mask = S2MPS11_IRQ_JIGONBF_MASK,
155-
},
156-
[S2MPS14_IRQ_JIGONBR] = {
157-
.reg_offset = 0,
158-
.mask = S2MPS11_IRQ_JIGONBR_MASK,
159-
},
160-
[S2MPS14_IRQ_ACOKBF] = {
161-
.reg_offset = 0,
162-
.mask = S2MPS11_IRQ_ACOKBF_MASK,
163-
},
164-
[S2MPS14_IRQ_ACOKBR] = {
165-
.reg_offset = 0,
166-
.mask = S2MPS11_IRQ_ACOKBR_MASK,
167-
},
168-
[S2MPS14_IRQ_PWRON1S] = {
169-
.reg_offset = 0,
170-
.mask = S2MPS11_IRQ_PWRON1S_MASK,
171-
},
172-
[S2MPS14_IRQ_MRB] = {
173-
.reg_offset = 0,
174-
.mask = S2MPS11_IRQ_MRB_MASK,
175-
},
176-
[S2MPS14_IRQ_RTC60S] = {
177-
.reg_offset = 1,
178-
.mask = S2MPS11_IRQ_RTC60S_MASK,
179-
},
180-
[S2MPS14_IRQ_RTCA1] = {
181-
.reg_offset = 1,
182-
.mask = S2MPS11_IRQ_RTCA1_MASK,
183-
},
184-
[S2MPS14_IRQ_RTCA0] = {
185-
.reg_offset = 1,
186-
.mask = S2MPS11_IRQ_RTCA0_MASK,
187-
},
188-
[S2MPS14_IRQ_SMPL] = {
189-
.reg_offset = 1,
190-
.mask = S2MPS11_IRQ_SMPL_MASK,
191-
},
192-
[S2MPS14_IRQ_RTC1S] = {
193-
.reg_offset = 1,
194-
.mask = S2MPS11_IRQ_RTC1S_MASK,
195-
},
196-
[S2MPS14_IRQ_WTSR] = {
197-
.reg_offset = 1,
198-
.mask = S2MPS11_IRQ_WTSR_MASK,
199-
},
200-
[S2MPS14_IRQ_INT120C] = {
201-
.reg_offset = 2,
202-
.mask = S2MPS11_IRQ_INT120C_MASK,
203-
},
204-
[S2MPS14_IRQ_INT140C] = {
205-
.reg_offset = 2,
206-
.mask = S2MPS11_IRQ_INT140C_MASK,
207-
},
208-
[S2MPS14_IRQ_TSD] = {
209-
.reg_offset = 2,
210-
.mask = S2MPS14_IRQ_TSD_MASK,
211-
},
98+
REGMAP_IRQ_REG(S2MPS14_IRQ_PWRONF, 0, S2MPS11_IRQ_PWRONF_MASK),
99+
REGMAP_IRQ_REG(S2MPS14_IRQ_PWRONR, 0, S2MPS11_IRQ_PWRONR_MASK),
100+
REGMAP_IRQ_REG(S2MPS14_IRQ_JIGONBF, 0, S2MPS11_IRQ_JIGONBF_MASK),
101+
REGMAP_IRQ_REG(S2MPS14_IRQ_JIGONBR, 0, S2MPS11_IRQ_JIGONBR_MASK),
102+
REGMAP_IRQ_REG(S2MPS14_IRQ_ACOKBF, 0, S2MPS11_IRQ_ACOKBF_MASK),
103+
REGMAP_IRQ_REG(S2MPS14_IRQ_ACOKBR, 0, S2MPS11_IRQ_ACOKBR_MASK),
104+
REGMAP_IRQ_REG(S2MPS14_IRQ_PWRON1S, 0, S2MPS11_IRQ_PWRON1S_MASK),
105+
REGMAP_IRQ_REG(S2MPS14_IRQ_MRB, 0, S2MPS11_IRQ_MRB_MASK),
106+
107+
REGMAP_IRQ_REG(S2MPS14_IRQ_RTC60S, 1, S2MPS11_IRQ_RTC60S_MASK),
108+
REGMAP_IRQ_REG(S2MPS14_IRQ_RTCA1, 1, S2MPS11_IRQ_RTCA1_MASK),
109+
REGMAP_IRQ_REG(S2MPS14_IRQ_RTCA0, 1, S2MPS11_IRQ_RTCA0_MASK),
110+
REGMAP_IRQ_REG(S2MPS14_IRQ_SMPL, 1, S2MPS11_IRQ_SMPL_MASK),
111+
REGMAP_IRQ_REG(S2MPS14_IRQ_RTC1S, 1, S2MPS11_IRQ_RTC1S_MASK),
112+
REGMAP_IRQ_REG(S2MPS14_IRQ_WTSR, 1, S2MPS11_IRQ_WTSR_MASK),
113+
114+
REGMAP_IRQ_REG(S2MPS14_IRQ_INT120C, 2, S2MPS11_IRQ_INT120C_MASK),
115+
REGMAP_IRQ_REG(S2MPS14_IRQ_INT140C, 2, S2MPS11_IRQ_INT140C_MASK),
116+
REGMAP_IRQ_REG(S2MPS14_IRQ_TSD, 2, S2MPS14_IRQ_TSD_MASK),
212117
};
213118

214119
static const struct regmap_irq s2mpu02_irqs[] = {
215-
[S2MPU02_IRQ_PWRONF] = {
216-
.reg_offset = 0,
217-
.mask = S2MPS11_IRQ_PWRONF_MASK,
218-
},
219-
[S2MPU02_IRQ_PWRONR] = {
220-
.reg_offset = 0,
221-
.mask = S2MPS11_IRQ_PWRONR_MASK,
222-
},
223-
[S2MPU02_IRQ_JIGONBF] = {
224-
.reg_offset = 0,
225-
.mask = S2MPS11_IRQ_JIGONBF_MASK,
226-
},
227-
[S2MPU02_IRQ_JIGONBR] = {
228-
.reg_offset = 0,
229-
.mask = S2MPS11_IRQ_JIGONBR_MASK,
230-
},
231-
[S2MPU02_IRQ_ACOKBF] = {
232-
.reg_offset = 0,
233-
.mask = S2MPS11_IRQ_ACOKBF_MASK,
234-
},
235-
[S2MPU02_IRQ_ACOKBR] = {
236-
.reg_offset = 0,
237-
.mask = S2MPS11_IRQ_ACOKBR_MASK,
238-
},
239-
[S2MPU02_IRQ_PWRON1S] = {
240-
.reg_offset = 0,
241-
.mask = S2MPS11_IRQ_PWRON1S_MASK,
242-
},
243-
[S2MPU02_IRQ_MRB] = {
244-
.reg_offset = 0,
245-
.mask = S2MPS11_IRQ_MRB_MASK,
246-
},
247-
[S2MPU02_IRQ_RTC60S] = {
248-
.reg_offset = 1,
249-
.mask = S2MPS11_IRQ_RTC60S_MASK,
250-
},
251-
[S2MPU02_IRQ_RTCA1] = {
252-
.reg_offset = 1,
253-
.mask = S2MPS11_IRQ_RTCA1_MASK,
254-
},
255-
[S2MPU02_IRQ_RTCA0] = {
256-
.reg_offset = 1,
257-
.mask = S2MPS11_IRQ_RTCA0_MASK,
258-
},
259-
[S2MPU02_IRQ_SMPL] = {
260-
.reg_offset = 1,
261-
.mask = S2MPS11_IRQ_SMPL_MASK,
262-
},
263-
[S2MPU02_IRQ_RTC1S] = {
264-
.reg_offset = 1,
265-
.mask = S2MPS11_IRQ_RTC1S_MASK,
266-
},
267-
[S2MPU02_IRQ_WTSR] = {
268-
.reg_offset = 1,
269-
.mask = S2MPS11_IRQ_WTSR_MASK,
270-
},
271-
[S2MPU02_IRQ_INT120C] = {
272-
.reg_offset = 2,
273-
.mask = S2MPS11_IRQ_INT120C_MASK,
274-
},
275-
[S2MPU02_IRQ_INT140C] = {
276-
.reg_offset = 2,
277-
.mask = S2MPS11_IRQ_INT140C_MASK,
278-
},
279-
[S2MPU02_IRQ_TSD] = {
280-
.reg_offset = 2,
281-
.mask = S2MPS14_IRQ_TSD_MASK,
282-
},
120+
REGMAP_IRQ_REG(S2MPU02_IRQ_PWRONF, 0, S2MPS11_IRQ_PWRONF_MASK),
121+
REGMAP_IRQ_REG(S2MPU02_IRQ_PWRONR, 0, S2MPS11_IRQ_PWRONR_MASK),
122+
REGMAP_IRQ_REG(S2MPU02_IRQ_JIGONBF, 0, S2MPS11_IRQ_JIGONBF_MASK),
123+
REGMAP_IRQ_REG(S2MPU02_IRQ_JIGONBR, 0, S2MPS11_IRQ_JIGONBR_MASK),
124+
REGMAP_IRQ_REG(S2MPU02_IRQ_ACOKBF, 0, S2MPS11_IRQ_ACOKBF_MASK),
125+
REGMAP_IRQ_REG(S2MPU02_IRQ_ACOKBR, 0, S2MPS11_IRQ_ACOKBR_MASK),
126+
REGMAP_IRQ_REG(S2MPU02_IRQ_PWRON1S, 0, S2MPS11_IRQ_PWRON1S_MASK),
127+
REGMAP_IRQ_REG(S2MPU02_IRQ_MRB, 0, S2MPS11_IRQ_MRB_MASK),
128+
129+
REGMAP_IRQ_REG(S2MPU02_IRQ_RTC60S, 1, S2MPS11_IRQ_RTC60S_MASK),
130+
REGMAP_IRQ_REG(S2MPU02_IRQ_RTCA1, 1, S2MPS11_IRQ_RTCA1_MASK),
131+
REGMAP_IRQ_REG(S2MPU02_IRQ_RTCA0, 1, S2MPS11_IRQ_RTCA0_MASK),
132+
REGMAP_IRQ_REG(S2MPU02_IRQ_SMPL, 1, S2MPS11_IRQ_SMPL_MASK),
133+
REGMAP_IRQ_REG(S2MPU02_IRQ_RTC1S, 1, S2MPS11_IRQ_RTC1S_MASK),
134+
REGMAP_IRQ_REG(S2MPU02_IRQ_WTSR, 1, S2MPS11_IRQ_WTSR_MASK),
135+
136+
REGMAP_IRQ_REG(S2MPU02_IRQ_INT120C, 2, S2MPS11_IRQ_INT120C_MASK),
137+
REGMAP_IRQ_REG(S2MPU02_IRQ_INT140C, 2, S2MPS11_IRQ_INT140C_MASK),
138+
REGMAP_IRQ_REG(S2MPU02_IRQ_TSD, 2, S2MPS14_IRQ_TSD_MASK),
283139
};
284140

285141
static const struct regmap_irq s2mpu05_irqs[] = {
@@ -303,74 +159,25 @@ static const struct regmap_irq s2mpu05_irqs[] = {
303159
};
304160

305161
static const struct regmap_irq s5m8767_irqs[] = {
306-
[S5M8767_IRQ_PWRR] = {
307-
.reg_offset = 0,
308-
.mask = S5M8767_IRQ_PWRR_MASK,
309-
},
310-
[S5M8767_IRQ_PWRF] = {
311-
.reg_offset = 0,
312-
.mask = S5M8767_IRQ_PWRF_MASK,
313-
},
314-
[S5M8767_IRQ_PWR1S] = {
315-
.reg_offset = 0,
316-
.mask = S5M8767_IRQ_PWR1S_MASK,
317-
},
318-
[S5M8767_IRQ_JIGR] = {
319-
.reg_offset = 0,
320-
.mask = S5M8767_IRQ_JIGR_MASK,
321-
},
322-
[S5M8767_IRQ_JIGF] = {
323-
.reg_offset = 0,
324-
.mask = S5M8767_IRQ_JIGF_MASK,
325-
},
326-
[S5M8767_IRQ_LOWBAT2] = {
327-
.reg_offset = 0,
328-
.mask = S5M8767_IRQ_LOWBAT2_MASK,
329-
},
330-
[S5M8767_IRQ_LOWBAT1] = {
331-
.reg_offset = 0,
332-
.mask = S5M8767_IRQ_LOWBAT1_MASK,
333-
},
334-
[S5M8767_IRQ_MRB] = {
335-
.reg_offset = 1,
336-
.mask = S5M8767_IRQ_MRB_MASK,
337-
},
338-
[S5M8767_IRQ_DVSOK2] = {
339-
.reg_offset = 1,
340-
.mask = S5M8767_IRQ_DVSOK2_MASK,
341-
},
342-
[S5M8767_IRQ_DVSOK3] = {
343-
.reg_offset = 1,
344-
.mask = S5M8767_IRQ_DVSOK3_MASK,
345-
},
346-
[S5M8767_IRQ_DVSOK4] = {
347-
.reg_offset = 1,
348-
.mask = S5M8767_IRQ_DVSOK4_MASK,
349-
},
350-
[S5M8767_IRQ_RTC60S] = {
351-
.reg_offset = 2,
352-
.mask = S5M8767_IRQ_RTC60S_MASK,
353-
},
354-
[S5M8767_IRQ_RTCA1] = {
355-
.reg_offset = 2,
356-
.mask = S5M8767_IRQ_RTCA1_MASK,
357-
},
358-
[S5M8767_IRQ_RTCA2] = {
359-
.reg_offset = 2,
360-
.mask = S5M8767_IRQ_RTCA2_MASK,
361-
},
362-
[S5M8767_IRQ_SMPL] = {
363-
.reg_offset = 2,
364-
.mask = S5M8767_IRQ_SMPL_MASK,
365-
},
366-
[S5M8767_IRQ_RTC1S] = {
367-
.reg_offset = 2,
368-
.mask = S5M8767_IRQ_RTC1S_MASK,
369-
},
370-
[S5M8767_IRQ_WTSR] = {
371-
.reg_offset = 2,
372-
.mask = S5M8767_IRQ_WTSR_MASK,
373-
},
162+
REGMAP_IRQ_REG(S5M8767_IRQ_PWRR, 0, S5M8767_IRQ_PWRR_MASK),
163+
REGMAP_IRQ_REG(S5M8767_IRQ_PWRF, 0, S5M8767_IRQ_PWRF_MASK),
164+
REGMAP_IRQ_REG(S5M8767_IRQ_PWR1S, 0, S5M8767_IRQ_PWR1S_MASK),
165+
REGMAP_IRQ_REG(S5M8767_IRQ_JIGR, 0, S5M8767_IRQ_JIGR_MASK),
166+
REGMAP_IRQ_REG(S5M8767_IRQ_JIGF, 0, S5M8767_IRQ_JIGF_MASK),
167+
REGMAP_IRQ_REG(S5M8767_IRQ_LOWBAT2, 0, S5M8767_IRQ_LOWBAT2_MASK),
168+
REGMAP_IRQ_REG(S5M8767_IRQ_LOWBAT1, 0, S5M8767_IRQ_LOWBAT1_MASK),
169+
170+
REGMAP_IRQ_REG(S5M8767_IRQ_MRB, 1, S5M8767_IRQ_MRB_MASK),
171+
REGMAP_IRQ_REG(S5M8767_IRQ_DVSOK2, 1, S5M8767_IRQ_DVSOK2_MASK),
172+
REGMAP_IRQ_REG(S5M8767_IRQ_DVSOK3, 1, S5M8767_IRQ_DVSOK3_MASK),
173+
REGMAP_IRQ_REG(S5M8767_IRQ_DVSOK4, 1, S5M8767_IRQ_DVSOK4_MASK),
174+
175+
REGMAP_IRQ_REG(S5M8767_IRQ_RTC60S, 2, S5M8767_IRQ_RTC60S_MASK),
176+
REGMAP_IRQ_REG(S5M8767_IRQ_RTCA1, 2, S5M8767_IRQ_RTCA1_MASK),
177+
REGMAP_IRQ_REG(S5M8767_IRQ_RTCA2, 2, S5M8767_IRQ_RTCA2_MASK),
178+
REGMAP_IRQ_REG(S5M8767_IRQ_SMPL, 2, S5M8767_IRQ_SMPL_MASK),
179+
REGMAP_IRQ_REG(S5M8767_IRQ_RTC1S, 2, S5M8767_IRQ_RTC1S_MASK),
180+
REGMAP_IRQ_REG(S5M8767_IRQ_WTSR, 2, S5M8767_IRQ_WTSR_MASK),
374181
};
375182

376183
/* All S2MPG10 interrupt sources are read-only and don't require clearing */

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