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Merge tag 'soc-drivers-6.19-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull more SoC driver updates from Arnd Bergmann: "These updates came a little late, or were based on a later 6.18-rc tag than the others: - A new driver for cache management on cxl devices with memory shared in a coherent cluster. This is part of the drivers/cache/ tree, but unlike the other drivers that back the dma-mapping interfaces, this one is needed only during CPU hotplug. - A shared branch for reset controllers using swnode infrastructure - Added support for new SoC variants in the Amlogic soc_device identification - Minor updates in Freescale, Microchip, Samsung, and Apple SoC drivers" * tag 'soc-drivers-6.19-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (24 commits) soc: samsung: exynos-pmu: fix device leak on regmap lookup soc: samsung: exynos-pmu: Fix structure initialization soc: fsl: qbman: use kmalloc_array() instead of kmalloc() soc: fsl: qbman: add WQ_PERCPU to alloc_workqueue users MAINTAINERS: Update email address for Christophe Leroy MAINTAINERS: refer to intended file in STANDALONE CACHE CONTROLLER DRIVERS cache: Support cache maintenance for HiSilicon SoC Hydra Home Agent cache: Make top level Kconfig menu a boolean dependent on RISCV MAINTAINERS: Add Jonathan Cameron to drivers/cache and add lib/cache_maint.c + header arm64: Select GENERIC_CPU_CACHE_MAINTENANCE lib: Support ARCH_HAS_CPU_CACHE_INVALIDATE_MEMREGION soc: amlogic: meson-gx-socinfo: add new SoCs id dt-bindings: arm: amlogic: meson-gx-ao-secure: support more SoCs memregion: Support fine grained invalidate by cpu_cache_invalidate_memregion() memregion: Drop unused IORES_DESC_* parameter from cpu_cache_invalidate_memregion() dt-bindings: cache: sifive,ccache0: add a pic64gx compatible MAINTAINERS: rename Microchip RISC-V entry MAINTAINERS: add new soc drivers to Microchip RISC-V entry soc: microchip: add mfd drivers for two syscon regions on PolarFire SoC dt-bindings: soc: microchip: document the simple-mfd syscon on PolarFire SoC ...
2 parents 208eed9 + 68f9bbf commit 11efc1c

29 files changed

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‎.mailmap‎

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@@ -186,6 +186,9 @@ Christian Brauner <brauner@kernel.org> <christian@brauner.io>
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Christian Brauner <brauner@kernel.org> <christian.brauner@canonical.com>
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Christian Brauner <brauner@kernel.org> <christian.brauner@ubuntu.com>
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Christian Marangi <ansuelsmth@gmail.com>
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Christophe Leroy <chleroy@kernel.org> <christophe.leroy@c-s.fr>
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Christophe Leroy <chleroy@kernel.org> <christophe.leroy@csgroup.eu>
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Christophe Leroy <chleroy@kernel.org> <christophe.leroy2@cs-soprasteria.com>
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Christophe Ricard <christophe.ricard@gmail.com>
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Christopher Obbard <christopher.obbard@linaro.org> <chris.obbard@collabora.com>
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Christoph Hellwig <hch@lst.de>

‎Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml‎

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- amlogic,a4-ao-secure
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- amlogic,c3-ao-secure
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- amlogic,s4-ao-secure
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- amlogic,s6-ao-secure
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- amlogic,s7-ao-secure
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- amlogic,s7d-ao-secure
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- amlogic,t7-ao-secure
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- const: amlogic,meson-gx-ao-secure
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- const: syscon

‎Documentation/devicetree/bindings/cache/sifive,ccache0.yaml‎

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- const: microchip,mpfs-ccache
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- const: sifive,fu540-c000-ccache
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- const: cache
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- items:
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- const: microchip,pic64gx-ccache
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- const: microchip,mpfs-ccache
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- const: sifive,fu540-c000-ccache
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- const: cache
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cache-block-size:
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const: 64

‎Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-mss-top-sysreg.yaml‎

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/soc/microchip/microchip,mpfs-mss-top-sysreg.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Microchip PolarFire SoC Microprocessor Subsystem (MSS) sysreg register region
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maintainers:
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- Conor Dooley <conor.dooley@microchip.com>
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description:
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An wide assortment of registers that control elements of the MSS on PolarFire
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SoC, including pinmuxing, resets and clocks among others.
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properties:
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compatible:
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items:
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- const: microchip,mpfs-mss-top-sysreg
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- const: syscon
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reg:
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maxItems: 1
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'#reset-cells':
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description:
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The AHB/AXI peripherals on the PolarFire SoC have reset support, so
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from CLK_ENVM to CLK_CFM. The reset consumer should specify the
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desired peripheral via the clock ID in its "resets" phandle cell.
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See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list
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of PolarFire clock/reset IDs.
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const: 1
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required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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- |
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syscon@20002000 {
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compatible = "microchip,mpfs-mss-top-sysreg", "syscon";
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reg = <0x20002000 0x1000>;
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#reset-cells = <1>;
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};
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‎MAINTAINERS‎

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BPF JIT for POWERPC (32-BIT AND 64-BIT)
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M: Hari Bathini <hbathini@linux.ibm.com>
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M: Christophe Leroy <christophe.leroy@csgroup.eu>
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M: Christophe Leroy (CS GROUP) <chleroy@kernel.org>
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R: Naveen N Rao <naveen@kernel.org>
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L: bpf@vger.kernel.org
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S: Supported
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FREESCALE QUICC ENGINE LIBRARY
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M: Qiang Zhao <qiang.zhao@nxp.com>
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M: Christophe Leroy <christophe.leroy@csgroup.eu>
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M: Christophe Leroy (CS GROUP) <chleroy@kernel.org>
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L: linuxppc-dev@lists.ozlabs.org
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S: Maintained
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F: drivers/soc/fsl/qe/
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F: drivers/tty/serial/ucc_uart.c
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FREESCALE SOC DRIVERS
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M: Christophe Leroy <christophe.leroy@csgroup.eu>
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M: Christophe Leroy (CS GROUP) <chleroy@kernel.org>
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L: linuxppc-dev@lists.ozlabs.org
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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S: Maintained
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M: Madhavan Srinivasan <maddy@linux.ibm.com>
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M: Michael Ellerman <mpe@ellerman.id.au>
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R: Nicholas Piggin <npiggin@gmail.com>
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R: Christophe Leroy <christophe.leroy@csgroup.eu>
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R: Christophe Leroy (CS GROUP) <chleroy@kernel.org>
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S: Supported
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W: https://github.com/linuxppc/wiki/wiki
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F: arch/powerpc/platforms/85xx/
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LINUX FOR POWERPC EMBEDDED PPC8XX AND PPC83XX
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M: Christophe Leroy <christophe.leroy@csgroup.eu>
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M: Christophe Leroy (CS GROUP) <chleroy@kernel.org>
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F: arch/powerpc/platforms/8xx/
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F: Documentation/devicetree/bindings/iommu/riscv,iommu.yaml
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F: drivers/iommu/riscv/
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RISC-V MICROCHIP FPGA SUPPORT
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RISC-V MICROCHIP SUPPORT
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M: Conor Dooley <conor.dooley@microchip.com>
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M: Daire McNamara <daire.mcnamara@microchip.com>
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L: linux-riscv@lists.infradead.org
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F: drivers/pwm/pwm-microchip-core.c
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F: drivers/reset/reset-mpfs.c
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F: drivers/rtc/rtc-mpfs.c
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F: drivers/soc/microchip/mpfs-control-scb.c
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F: drivers/soc/microchip/mpfs-mss-top-sysreg.c
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F: drivers/soc/microchip/mpfs-sys-controller.c
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F: drivers/spi/spi-microchip-core-qspi.c
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F: drivers/spi/spi-mpfs.c
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STANDALONE CACHE CONTROLLER DRIVERS
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M: Jonathan Cameron <jonathan.cameron@huawei.com>
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S: Maintained
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F: Documentation/devicetree/bindings/cache/
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F: drivers/cache
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F: include/linux/cache_coherency.h
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F: lib/cache_maint.c
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STARFIRE/DURALAN NETWORK DRIVER
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‎arch/arm64/Kconfig‎

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select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE
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select ARCH_HAS_CACHE_LINE_SIZE
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select ARCH_HAS_CC_PLATFORM
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select ARCH_HAS_CPU_CACHE_INVALIDATE_MEMREGION
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select ARCH_HAS_CURRENT_STACK_POINTER
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select ARCH_HAS_DEBUG_VIRTUAL
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select ARCH_HAS_DEBUG_VM_PGTABLE
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select GENERIC_ARCH_TOPOLOGY
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select GENERIC_CPU_CACHE_MAINTENANCE
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select GENERIC_CPU_DEVICES
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select GENERIC_EARLY_IOREMAP

‎arch/x86/mm/pat/set_memory.c‎

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}
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EXPORT_SYMBOL_NS_GPL(cpu_cache_has_invalidate_memregion, "DEVMEM");
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int cpu_cache_invalidate_memregion(int res_desc)
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int cpu_cache_invalidate_memregion(phys_addr_t start, size_t len)
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{
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if (WARN_ON_ONCE(!cpu_cache_has_invalidate_memregion()))
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return -ENXIO;

‎drivers/cache/Kconfig‎

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# SPDX-License-Identifier: GPL-2.0
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menu "Cache Drivers"
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menuconfig CACHEMAINT_FOR_DMA
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bool "Cache management for noncoherent DMA"
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depends on RISCV
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default y
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help
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These drivers implement support for noncoherent DMA master devices
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on platforms that lack the standard CPU interfaces for this.
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if CACHEMAINT_FOR_DMA
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config AX45MP_L2_CACHE
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bool "Andes Technology AX45MP L2 Cache controller"
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depends on RISCV
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select RISCV_NONSTANDARD_CACHE_OPS
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help
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Support for the L2 cache controller on Andes Technology AX45MP platforms.
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config STARFIVE_STARLINK_CACHE
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bool "StarFive StarLink Cache controller"
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depends on RISCV
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depends on ARCH_STARFIVE
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depends on 64BIT
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select RISCV_DMA_NONCOHERENT
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select RISCV_NONSTANDARD_CACHE_OPS
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help
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Support for the StarLink cache controller IP from StarFive.
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endmenu
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endif #CACHEMAINT_FOR_DMA
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menuconfig CACHEMAINT_FOR_HOTPLUG
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bool "Cache management for memory hot plug like operations"
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depends on GENERIC_CPU_CACHE_MAINTENANCE
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help
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These drivers implement cache management for flows where it is necessary
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to flush data from all host caches.
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if CACHEMAINT_FOR_HOTPLUG
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config HISI_SOC_HHA
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tristate "HiSilicon Hydra Home Agent (HHA) device driver"
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depends on (ARM64 && ACPI) || COMPILE_TEST
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help
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The Hydra Home Agent (HHA) is responsible for cache coherency
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on the SoC. This drivers enables the cache maintenance functions of
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the HHA.
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This driver can be built as a module. If so, the module will be
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called hisi_soc_hha.
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endif #CACHEMAINT_FOR_HOTPLUG

‎drivers/cache/Makefile‎

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obj-$(CONFIG_AX45MP_L2_CACHE) += ax45mp_cache.o
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obj-$(CONFIG_SIFIVE_CCACHE) += sifive_ccache.o
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obj-$(CONFIG_STARFIVE_STARLINK_CACHE) += starfive_starlink_cache.o
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obj-$(CONFIG_HISI_SOC_HHA) += hisi_soc_hha.o

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