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airliedairlied
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Merge tag 'drm-msm-next-2021-02-07' of https://gitlab.freedesktop.org/drm/msm into drm-next
* a6xx speedbin support * a508, a509, a512 support * various a5xx fixes * various dpu fixes * qseed3lite support for sm8250 * dsi fix for msm8994 * mdp5 fix for framerate bug with cmd mode panels * a6xx GMU OOB race fixes that were showing up in CI * various addition and removal of semicolons * gem submit fix for legacy userspace relocs path Signed-off-by: Dave Airlie <airlied@redhat.com> From: Rob Clark <robdclark@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/CAF6AEGvh3tvLz_xtk=4x9xUfo2h2s4xkniOvC7HyLO2jrXnXkw@mail.gmail.com
2 parents f730f39 + 182b4a2 commit 12458e3

36 files changed

Lines changed: 803 additions & 219 deletions

‎drivers/gpu/drm/msm/adreno/a5xx.xml.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2367,6 +2367,8 @@ static inline uint32_t A5XX_VSC_RESOLVE_CNTL_Y(uint32_t val)
23672367

23682368
#define REG_A5XX_UCHE_ADDR_MODE_CNTL 0x00000e80
23692369

2370+
#define REG_A5XX_UCHE_MODE_CNTL 0x00000e81
2371+
23702372
#define REG_A5XX_UCHE_SVM_CNTL 0x00000e82
23712373

23722374
#define REG_A5XX_UCHE_WRITE_THRU_BASE_LO 0x00000e87

‎drivers/gpu/drm/msm/adreno/a5xx_gpu.c‎

Lines changed: 170 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -222,7 +222,7 @@ static void a5xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
222222
a5xx_preempt_trigger(gpu);
223223
}
224224

225-
static const struct {
225+
static const struct adreno_five_hwcg_regs {
226226
u32 offset;
227227
u32 value;
228228
} a5xx_hwcg[] = {
@@ -318,16 +318,124 @@ static const struct {
318318
{REG_A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
319319
{REG_A5XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
320320
{REG_A5XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}
321+
}, a50x_hwcg[] = {
322+
{REG_A5XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
323+
{REG_A5XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
324+
{REG_A5XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
325+
{REG_A5XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
326+
{REG_A5XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},
327+
{REG_A5XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
328+
{REG_A5XX_RBBM_CLOCK_CNTL3_TP0, 0x00002222},
329+
{REG_A5XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
330+
{REG_A5XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
331+
{REG_A5XX_RBBM_CLOCK_HYST3_TP0, 0x00007777},
332+
{REG_A5XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
333+
{REG_A5XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
334+
{REG_A5XX_RBBM_CLOCK_DELAY3_TP0, 0x00001111},
335+
{REG_A5XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222},
336+
{REG_A5XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222},
337+
{REG_A5XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222},
338+
{REG_A5XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
339+
{REG_A5XX_RBBM_CLOCK_HYST_UCHE, 0x00FFFFF4},
340+
{REG_A5XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
341+
{REG_A5XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
342+
{REG_A5XX_RBBM_CLOCK_CNTL2_RB0, 0x00222222},
343+
{REG_A5XX_RBBM_CLOCK_CNTL_CCU0, 0x00022220},
344+
{REG_A5XX_RBBM_CLOCK_CNTL_RAC, 0x05522222},
345+
{REG_A5XX_RBBM_CLOCK_CNTL2_RAC, 0x00505555},
346+
{REG_A5XX_RBBM_CLOCK_HYST_RB_CCU0, 0x04040404},
347+
{REG_A5XX_RBBM_CLOCK_HYST_RAC, 0x07444044},
348+
{REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_0, 0x00000002},
349+
{REG_A5XX_RBBM_CLOCK_DELAY_RAC, 0x00010011},
350+
{REG_A5XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
351+
{REG_A5XX_RBBM_CLOCK_MODE_GPC, 0x02222222},
352+
{REG_A5XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
353+
{REG_A5XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
354+
{REG_A5XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
355+
{REG_A5XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
356+
{REG_A5XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
357+
{REG_A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
358+
{REG_A5XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
359+
{REG_A5XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
360+
}, a512_hwcg[] = {
361+
{REG_A5XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
362+
{REG_A5XX_RBBM_CLOCK_CNTL_SP1, 0x02222222},
363+
{REG_A5XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
364+
{REG_A5XX_RBBM_CLOCK_CNTL2_SP1, 0x02222220},
365+
{REG_A5XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
366+
{REG_A5XX_RBBM_CLOCK_HYST_SP1, 0x0000F3CF},
367+
{REG_A5XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
368+
{REG_A5XX_RBBM_CLOCK_DELAY_SP1, 0x00000080},
369+
{REG_A5XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},
370+
{REG_A5XX_RBBM_CLOCK_CNTL_TP1, 0x22222222},
371+
{REG_A5XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
372+
{REG_A5XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222},
373+
{REG_A5XX_RBBM_CLOCK_CNTL3_TP0, 0x00002222},
374+
{REG_A5XX_RBBM_CLOCK_CNTL3_TP1, 0x00002222},
375+
{REG_A5XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
376+
{REG_A5XX_RBBM_CLOCK_HYST_TP1, 0x77777777},
377+
{REG_A5XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
378+
{REG_A5XX_RBBM_CLOCK_HYST2_TP1, 0x77777777},
379+
{REG_A5XX_RBBM_CLOCK_HYST3_TP0, 0x00007777},
380+
{REG_A5XX_RBBM_CLOCK_HYST3_TP1, 0x00007777},
381+
{REG_A5XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
382+
{REG_A5XX_RBBM_CLOCK_DELAY_TP1, 0x11111111},
383+
{REG_A5XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
384+
{REG_A5XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111},
385+
{REG_A5XX_RBBM_CLOCK_DELAY3_TP0, 0x00001111},
386+
{REG_A5XX_RBBM_CLOCK_DELAY3_TP1, 0x00001111},
387+
{REG_A5XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
388+
{REG_A5XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222},
389+
{REG_A5XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222},
390+
{REG_A5XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222},
391+
{REG_A5XX_RBBM_CLOCK_HYST_UCHE, 0x00444444},
392+
{REG_A5XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
393+
{REG_A5XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
394+
{REG_A5XX_RBBM_CLOCK_CNTL_RB1, 0x22222222},
395+
{REG_A5XX_RBBM_CLOCK_CNTL2_RB0, 0x00222222},
396+
{REG_A5XX_RBBM_CLOCK_CNTL2_RB1, 0x00222222},
397+
{REG_A5XX_RBBM_CLOCK_CNTL_CCU0, 0x00022220},
398+
{REG_A5XX_RBBM_CLOCK_CNTL_CCU1, 0x00022220},
399+
{REG_A5XX_RBBM_CLOCK_CNTL_RAC, 0x05522222},
400+
{REG_A5XX_RBBM_CLOCK_CNTL2_RAC, 0x00505555},
401+
{REG_A5XX_RBBM_CLOCK_HYST_RB_CCU0, 0x04040404},
402+
{REG_A5XX_RBBM_CLOCK_HYST_RB_CCU1, 0x04040404},
403+
{REG_A5XX_RBBM_CLOCK_HYST_RAC, 0x07444044},
404+
{REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_0, 0x00000002},
405+
{REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_1, 0x00000002},
406+
{REG_A5XX_RBBM_CLOCK_DELAY_RAC, 0x00010011},
407+
{REG_A5XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
408+
{REG_A5XX_RBBM_CLOCK_MODE_GPC, 0x02222222},
409+
{REG_A5XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
410+
{REG_A5XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
411+
{REG_A5XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
412+
{REG_A5XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
413+
{REG_A5XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
414+
{REG_A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
415+
{REG_A5XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
416+
{REG_A5XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
321417
};
322418

323419
void a5xx_set_hwcg(struct msm_gpu *gpu, bool state)
324420
{
325421
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
326-
unsigned int i;
422+
const struct adreno_five_hwcg_regs *regs;
423+
unsigned int i, sz;
424+
425+
if (adreno_is_a508(adreno_gpu)) {
426+
regs = a50x_hwcg;
427+
sz = ARRAY_SIZE(a50x_hwcg);
428+
} else if (adreno_is_a509(adreno_gpu) || adreno_is_a512(adreno_gpu)) {
429+
regs = a512_hwcg;
430+
sz = ARRAY_SIZE(a512_hwcg);
431+
} else {
432+
regs = a5xx_hwcg;
433+
sz = ARRAY_SIZE(a5xx_hwcg);
434+
}
327435

328-
for (i = 0; i < ARRAY_SIZE(a5xx_hwcg); i++)
329-
gpu_write(gpu, a5xx_hwcg[i].offset,
330-
state ? a5xx_hwcg[i].value : 0);
436+
for (i = 0; i < sz; i++)
437+
gpu_write(gpu, regs[i].offset,
438+
state ? regs[i].value : 0);
331439

332440
if (adreno_is_a540(adreno_gpu)) {
333441
gpu_write(gpu, REG_A5XX_RBBM_CLOCK_DELAY_GPMU, state ? 0x00000770 : 0);
@@ -538,11 +646,13 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
538646
{
539647
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
540648
struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu);
649+
u32 regbit;
541650
int ret;
542651

543652
gpu_write(gpu, REG_A5XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x00000003);
544653

545-
if (adreno_is_a540(adreno_gpu))
654+
if (adreno_is_a509(adreno_gpu) || adreno_is_a512(adreno_gpu) ||
655+
adreno_is_a540(adreno_gpu))
546656
gpu_write(gpu, REG_A5XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000009);
547657

548658
/* Make all blocks contribute to the GPU BUSY perf counter */
@@ -604,29 +714,48 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
604714
0x00100000 + adreno_gpu->gmem - 1);
605715
gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MAX_HI, 0x00000000);
606716

607-
if (adreno_is_a510(adreno_gpu)) {
717+
if (adreno_is_a508(adreno_gpu) || adreno_is_a510(adreno_gpu)) {
608718
gpu_write(gpu, REG_A5XX_CP_MEQ_THRESHOLDS, 0x20);
609-
gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x20);
719+
if (adreno_is_a508(adreno_gpu))
720+
gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x400);
721+
else
722+
gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x20);
610723
gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_2, 0x40000030);
611724
gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_1, 0x20100D0A);
612-
gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL,
613-
(0x200 << 11 | 0x200 << 22));
614725
} else {
615726
gpu_write(gpu, REG_A5XX_CP_MEQ_THRESHOLDS, 0x40);
616727
if (adreno_is_a530(adreno_gpu))
617728
gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x40);
618-
if (adreno_is_a540(adreno_gpu))
729+
else
619730
gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x400);
620731
gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_2, 0x80000060);
621732
gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_1, 0x40201B16);
733+
}
734+
735+
if (adreno_is_a508(adreno_gpu))
736+
gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL,
737+
(0x100 << 11 | 0x100 << 22));
738+
else if (adreno_is_a509(adreno_gpu) || adreno_is_a510(adreno_gpu) ||
739+
adreno_is_a512(adreno_gpu))
740+
gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL,
741+
(0x200 << 11 | 0x200 << 22));
742+
else
622743
gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL,
623744
(0x400 << 11 | 0x300 << 22));
624-
}
625745

626746
if (adreno_gpu->info->quirks & ADRENO_QUIRK_TWO_PASS_USE_WFI)
627747
gpu_rmw(gpu, REG_A5XX_PC_DBG_ECO_CNTL, 0, (1 << 8));
628748

629-
gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL, 0xc0200100);
749+
/*
750+
* Disable the RB sampler datapath DP2 clock gating optimization
751+
* for 1-SP GPUs, as it is enabled by default.
752+
*/
753+
if (adreno_is_a508(adreno_gpu) || adreno_is_a509(adreno_gpu) ||
754+
adreno_is_a512(adreno_gpu))
755+
gpu_rmw(gpu, REG_A5XX_RB_DBG_ECO_CNTL, 0, (1 << 9));
756+
757+
/* Disable UCHE global filter as SP can invalidate/flush independently */
758+
gpu_write(gpu, REG_A5XX_UCHE_MODE_CNTL, BIT(29));
630759

631760
/* Enable USE_RETENTION_FLOPS */
632761
gpu_write(gpu, REG_A5XX_CP_CHICKEN_DBG, 0x02000000);
@@ -653,10 +782,20 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
653782
gpu_write(gpu, REG_A5XX_RBBM_AHB_CNTL2, 0x0000003F);
654783

655784
/* Set the highest bank bit */
656-
gpu_write(gpu, REG_A5XX_TPL1_MODE_CNTL, 2 << 7);
657-
gpu_write(gpu, REG_A5XX_RB_MODE_CNTL, 2 << 1);
658785
if (adreno_is_a540(adreno_gpu))
659-
gpu_write(gpu, REG_A5XX_UCHE_DBG_ECO_CNTL_2, 2);
786+
regbit = 2;
787+
else
788+
regbit = 1;
789+
790+
gpu_write(gpu, REG_A5XX_TPL1_MODE_CNTL, regbit << 7);
791+
gpu_write(gpu, REG_A5XX_RB_MODE_CNTL, regbit << 1);
792+
793+
if (adreno_is_a509(adreno_gpu) || adreno_is_a512(adreno_gpu) ||
794+
adreno_is_a540(adreno_gpu))
795+
gpu_write(gpu, REG_A5XX_UCHE_DBG_ECO_CNTL_2, regbit);
796+
797+
/* Disable All flat shading optimization (ALLFLATOPTDIS) */
798+
gpu_rmw(gpu, REG_A5XX_VPC_DBG_ECO_CNTL, 0, (1 << 10));
660799

661800
/* Protect registers from the CP */
662801
gpu_write(gpu, REG_A5XX_CP_PROTECT_CNTL, 0x00000007);
@@ -688,12 +827,14 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
688827

689828
/* VPC */
690829
gpu_write(gpu, REG_A5XX_CP_PROTECT(14), ADRENO_PROTECT_RW(0xE68, 8));
691-
gpu_write(gpu, REG_A5XX_CP_PROTECT(15), ADRENO_PROTECT_RW(0xE70, 4));
830+
gpu_write(gpu, REG_A5XX_CP_PROTECT(15), ADRENO_PROTECT_RW(0xE70, 16));
692831

693832
/* UCHE */
694833
gpu_write(gpu, REG_A5XX_CP_PROTECT(16), ADRENO_PROTECT_RW(0xE80, 16));
695834

696-
if (adreno_is_a530(adreno_gpu) || adreno_is_a510(adreno_gpu))
835+
if (adreno_is_a508(adreno_gpu) || adreno_is_a509(adreno_gpu) ||
836+
adreno_is_a510(adreno_gpu) || adreno_is_a512(adreno_gpu) ||
837+
adreno_is_a530(adreno_gpu))
697838
gpu_write(gpu, REG_A5XX_CP_PROTECT(17),
698839
ADRENO_PROTECT_RW(0x10000, 0x8000));
699840

@@ -735,7 +876,8 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
735876
if (ret)
736877
return ret;
737878

738-
if (!adreno_is_a510(adreno_gpu))
879+
if (!(adreno_is_a508(adreno_gpu) || adreno_is_a509(adreno_gpu) ||
880+
adreno_is_a510(adreno_gpu) || adreno_is_a512(adreno_gpu)))
739881
a5xx_gpmu_ucode_init(gpu);
740882

741883
ret = a5xx_ucode_init(gpu);
@@ -1168,7 +1310,8 @@ static int a5xx_pm_resume(struct msm_gpu *gpu)
11681310
if (ret)
11691311
return ret;
11701312

1171-
if (adreno_is_a510(adreno_gpu)) {
1313+
/* Adreno 508, 509, 510, 512 needs manual RBBM sus/res control */
1314+
if (!(adreno_is_a530(adreno_gpu) || adreno_is_a540(adreno_gpu))) {
11721315
/* Halt the sp_input_clk at HM level */
11731316
gpu_write(gpu, REG_A5XX_RBBM_CLOCK_CNTL, 0x00000055);
11741317
a5xx_set_hwcg(gpu, true);
@@ -1210,8 +1353,8 @@ static int a5xx_pm_suspend(struct msm_gpu *gpu)
12101353
u32 mask = 0xf;
12111354
int i, ret;
12121355

1213-
/* A510 has 3 XIN ports in VBIF */
1214-
if (adreno_is_a510(adreno_gpu))
1356+
/* A508, A510 have 3 XIN ports in VBIF */
1357+
if (adreno_is_a508(adreno_gpu) || adreno_is_a510(adreno_gpu))
12151358
mask = 0x7;
12161359

12171360
/* Clear the VBIF pipe before shutting down */
@@ -1223,10 +1366,12 @@ static int a5xx_pm_suspend(struct msm_gpu *gpu)
12231366

12241367
/*
12251368
* Reset the VBIF before power collapse to avoid issue with FIFO
1226-
* entries
1369+
* entries on Adreno A510 and A530 (the others will tend to lock up)
12271370
*/
1228-
gpu_write(gpu, REG_A5XX_RBBM_BLOCK_SW_RESET_CMD, 0x003C0000);
1229-
gpu_write(gpu, REG_A5XX_RBBM_BLOCK_SW_RESET_CMD, 0x00000000);
1371+
if (adreno_is_a510(adreno_gpu) || adreno_is_a530(adreno_gpu)) {
1372+
gpu_write(gpu, REG_A5XX_RBBM_BLOCK_SW_RESET_CMD, 0x003C0000);
1373+
gpu_write(gpu, REG_A5XX_RBBM_BLOCK_SW_RESET_CMD, 0x00000000);
1374+
}
12301375

12311376
ret = msm_gpu_pm_suspend(gpu);
12321377
if (ret)

‎drivers/gpu/drm/msm/adreno/a5xx_power.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -298,7 +298,7 @@ int a5xx_power_init(struct msm_gpu *gpu)
298298
int ret;
299299

300300
/* Not all A5xx chips have a GPMU */
301-
if (adreno_is_a510(adreno_gpu))
301+
if (!(adreno_is_a530(adreno_gpu) || adreno_is_a540(adreno_gpu)))
302302
return 0;
303303

304304
/* Set up the limits management */
@@ -330,7 +330,7 @@ void a5xx_gpmu_ucode_init(struct msm_gpu *gpu)
330330
unsigned int *data, *ptr, *cmds;
331331
unsigned int cmds_size;
332332

333-
if (adreno_is_a510(adreno_gpu))
333+
if (!(adreno_is_a530(adreno_gpu) || adreno_is_a540(adreno_gpu)))
334334
return;
335335

336336
if (a5xx_gpu->gpmu_bo)

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