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prabhakarladgeertu
prabhakarlad
authored and
geertu
committed
pinctrl: renesas: rzg2l: Drop struct rzg2l_variable_pin_cfg
Drop the rzg2l_variable_pin_cfg struct and instead use the RZG2L_VARIABLE_PIN_CFG_PACK() macro for the variable pin configuration. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> # on RZ/G3S Link: https://lore.kernel.org/r/20240530173857.164073-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
1 parent 8081a03 commit 13a8cae

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Lines changed: 54 additions & 133 deletions

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‎drivers/pinctrl/renesas/pinctrl-rzg2l.c‎

Lines changed: 54 additions & 133 deletions
Original file line numberDiff line numberDiff line change
@@ -114,6 +114,13 @@
114114
FIELD_GET(RZG2L_SINGLE_PIN_INDEX_MASK, (cfg)) : \
115115
FIELD_GET(PIN_CFG_PIN_REG_MASK, (cfg)))
116116

117+
#define VARIABLE_PIN_CFG_PIN_MASK GENMASK_ULL(54, 52)
118+
#define VARIABLE_PIN_CFG_PORT_MASK GENMASK_ULL(51, 47)
119+
#define RZG2L_VARIABLE_PIN_CFG_PACK(port, pin, cfg) \
120+
(FIELD_PREP_CONST(VARIABLE_PIN_CFG_PIN_MASK, (pin)) | \
121+
FIELD_PREP_CONST(VARIABLE_PIN_CFG_PORT_MASK, (port)) | \
122+
FIELD_PREP_CONST(PIN_CFG_MASK, (cfg)))
123+
117124
#define P(off) (0x0000 + (off))
118125
#define PM(off) (0x0100 + (off) * 2)
119126
#define PMC(off) (0x0200 + (off))
@@ -234,18 +241,6 @@ struct rzg2l_dedicated_configs {
234241
u64 config;
235242
};
236243

237-
/**
238-
* struct rzg2l_variable_pin_cfg - pin data cfg
239-
* @cfg: port pin configuration
240-
* @port: port number
241-
* @pin: port pin
242-
*/
243-
struct rzg2l_variable_pin_cfg {
244-
u64 cfg:47;
245-
u64 port:5;
246-
u64 pin:3;
247-
};
248-
249244
struct rzg2l_pinctrl_data {
250245
const char * const *port_pins;
251246
const u64 *port_pin_configs;
@@ -254,7 +249,7 @@ struct rzg2l_pinctrl_data {
254249
unsigned int n_port_pins;
255250
unsigned int n_dedicated_pins;
256251
const struct rzg2l_hwcfg *hwcfg;
257-
const struct rzg2l_variable_pin_cfg *variable_pin_cfg;
252+
const u64 *variable_pin_cfg;
258253
unsigned int n_variable_pin_cfg;
259254
};
260255

@@ -331,131 +326,57 @@ static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl,
331326
unsigned int i;
332327

333328
for (i = 0; i < pctrl->data->n_variable_pin_cfg; i++) {
334-
if (pctrl->data->variable_pin_cfg[i].port == port &&
335-
pctrl->data->variable_pin_cfg[i].pin == pin)
336-
return (pincfg & ~PIN_CFG_VARIABLE) | pctrl->data->variable_pin_cfg[i].cfg;
329+
u64 cfg = pctrl->data->variable_pin_cfg[i];
330+
331+
if (FIELD_GET(VARIABLE_PIN_CFG_PORT_MASK, cfg) == port &&
332+
FIELD_GET(VARIABLE_PIN_CFG_PIN_MASK, cfg) == pin)
333+
return (pincfg & ~PIN_CFG_VARIABLE) | FIELD_GET(PIN_CFG_MASK, cfg);
337334
}
338335

339336
return 0;
340337
}
341338

342-
static const struct rzg2l_variable_pin_cfg r9a07g043f_variable_pin_cfg[] = {
343-
{
344-
.port = 20,
345-
.pin = 0,
346-
.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
347-
PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |
348-
PIN_CFG_IEN | PIN_CFG_NOGPIO_INT,
349-
},
350-
{
351-
.port = 20,
352-
.pin = 1,
353-
.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
354-
PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |
355-
PIN_CFG_IEN | PIN_CFG_NOGPIO_INT,
356-
},
357-
{
358-
.port = 20,
359-
.pin = 2,
360-
.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
361-
PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |
362-
PIN_CFG_IEN | PIN_CFG_NOGPIO_INT,
363-
},
364-
{
365-
.port = 20,
366-
.pin = 3,
367-
.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
368-
PIN_CFG_IEN | PIN_CFG_NOGPIO_INT,
369-
},
370-
{
371-
.port = 20,
372-
.pin = 4,
373-
.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
374-
PIN_CFG_IEN | PIN_CFG_NOGPIO_INT,
375-
},
376-
{
377-
.port = 20,
378-
.pin = 5,
379-
.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
380-
PIN_CFG_IEN | PIN_CFG_NOGPIO_INT,
381-
},
382-
{
383-
.port = 20,
384-
.pin = 6,
385-
.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
386-
PIN_CFG_IEN | PIN_CFG_NOGPIO_INT,
387-
},
388-
{
389-
.port = 20,
390-
.pin = 7,
391-
.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
392-
PIN_CFG_IEN | PIN_CFG_NOGPIO_INT,
393-
},
394-
{
395-
.port = 23,
396-
.pin = 1,
397-
.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
398-
PIN_CFG_NOGPIO_INT
399-
},
400-
{
401-
.port = 23,
402-
.pin = 2,
403-
.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
404-
PIN_CFG_NOGPIO_INT,
405-
},
406-
{
407-
.port = 23,
408-
.pin = 3,
409-
.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
410-
PIN_CFG_NOGPIO_INT,
411-
},
412-
{
413-
.port = 23,
414-
.pin = 4,
415-
.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
416-
PIN_CFG_NOGPIO_INT,
417-
},
418-
{
419-
.port = 23,
420-
.pin = 5,
421-
.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_NOGPIO_INT,
422-
},
423-
{
424-
.port = 24,
425-
.pin = 0,
426-
.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_NOGPIO_INT,
427-
},
428-
{
429-
.port = 24,
430-
.pin = 1,
431-
.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
432-
PIN_CFG_NOGPIO_INT,
433-
},
434-
{
435-
.port = 24,
436-
.pin = 2,
437-
.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
438-
PIN_CFG_NOGPIO_INT,
439-
},
440-
{
441-
.port = 24,
442-
.pin = 3,
443-
.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
444-
PIN_CFG_NOGPIO_INT,
445-
},
446-
{
447-
.port = 24,
448-
.pin = 4,
449-
.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
450-
PIN_CFG_NOGPIO_INT,
451-
},
452-
{
453-
.port = 24,
454-
.pin = 5,
455-
.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
456-
PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |
457-
PIN_CFG_NOGPIO_INT,
458-
},
339+
static const u64 r9a07g043f_variable_pin_cfg[] = {
340+
RZG2L_VARIABLE_PIN_CFG_PACK(20, 0, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
341+
PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |
342+
PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),
343+
RZG2L_VARIABLE_PIN_CFG_PACK(20, 1, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
344+
PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |
345+
PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),
346+
RZG2L_VARIABLE_PIN_CFG_PACK(20, 2, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
347+
PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |
348+
PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),
349+
RZG2L_VARIABLE_PIN_CFG_PACK(20, 3, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
350+
PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),
351+
RZG2L_VARIABLE_PIN_CFG_PACK(20, 4, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
352+
PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),
353+
RZG2L_VARIABLE_PIN_CFG_PACK(20, 5, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
354+
PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),
355+
RZG2L_VARIABLE_PIN_CFG_PACK(20, 6, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
356+
PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),
357+
RZG2L_VARIABLE_PIN_CFG_PACK(20, 7, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
358+
PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),
359+
RZG2L_VARIABLE_PIN_CFG_PACK(23, 1, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
360+
PIN_CFG_NOGPIO_INT),
361+
RZG2L_VARIABLE_PIN_CFG_PACK(23, 2, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
362+
PIN_CFG_NOGPIO_INT),
363+
RZG2L_VARIABLE_PIN_CFG_PACK(23, 3, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
364+
PIN_CFG_NOGPIO_INT),
365+
RZG2L_VARIABLE_PIN_CFG_PACK(23, 4, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
366+
PIN_CFG_NOGPIO_INT),
367+
RZG2L_VARIABLE_PIN_CFG_PACK(23, 5, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_NOGPIO_INT),
368+
RZG2L_VARIABLE_PIN_CFG_PACK(24, 0, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_NOGPIO_INT),
369+
RZG2L_VARIABLE_PIN_CFG_PACK(24, 1, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
370+
PIN_CFG_NOGPIO_INT),
371+
RZG2L_VARIABLE_PIN_CFG_PACK(24, 2, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
372+
PIN_CFG_NOGPIO_INT),
373+
RZG2L_VARIABLE_PIN_CFG_PACK(24, 3, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
374+
PIN_CFG_NOGPIO_INT),
375+
RZG2L_VARIABLE_PIN_CFG_PACK(24, 4, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
376+
PIN_CFG_NOGPIO_INT),
377+
RZG2L_VARIABLE_PIN_CFG_PACK(24, 5, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
378+
PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |
379+
PIN_CFG_NOGPIO_INT),
459380
};
460381
#endif
461382

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