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irqchip: Add RZ/{T2H,N2H} Interrupt Controller (ICU) driver
The Renesas RZ/T2H (R9A09G077) and Renesas RZ/N2H (R9A09G087) SoCs have an Interrupt Controller (ICU) that supports interrupts from external pins IRQ0 to IRQ15, and SEI, and software-triggered interrupts INTCPU0 to INTCPU15. INTCPU0 to INTCPU13, IRQ0 to IRQ13 are non-safety interrupts, while INTCPU14, INTCPU15, IRQ14, IRQ15 and SEI are safety interrupts, and are exposed via a separate register space. Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://patch.msgid.link/20251201112933.488801-3-cosmin-gabriel.tanislav.xa@renesas.com
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Lines changed: 313 additions & 0 deletions

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‎drivers/irqchip/Kconfig‎

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@@ -297,6 +297,14 @@ config RENESAS_RZG2L_IRQC
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Enable support for the Renesas RZ/G2L (and alike SoC) Interrupt Controller
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for external devices.
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300+
config RENESAS_RZT2H_ICU
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bool "Renesas RZ/{T2H,N2H} ICU support" if COMPILE_TEST
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN_HIERARCHY
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help
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Enable support for the Renesas RZ/{T2H,N2H} Interrupt Controller
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(ICU).
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config RENESAS_RZV2H_ICU
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bool "Renesas RZ/V2H(P) ICU support" if COMPILE_TEST
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select GENERIC_IRQ_CHIP

‎drivers/irqchip/Makefile‎

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Original file line numberDiff line numberDiff line change
@@ -54,6 +54,7 @@ obj-$(CONFIG_RENESAS_INTC_IRQPIN) += irq-renesas-intc-irqpin.o
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obj-$(CONFIG_RENESAS_IRQC) += irq-renesas-irqc.o
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obj-$(CONFIG_RENESAS_RZA1_IRQC) += irq-renesas-rza1.o
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obj-$(CONFIG_RENESAS_RZG2L_IRQC) += irq-renesas-rzg2l.o
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obj-$(CONFIG_RENESAS_RZT2H_ICU) += irq-renesas-rzt2h.o
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obj-$(CONFIG_RENESAS_RZV2H_ICU) += irq-renesas-rzv2h.o
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obj-$(CONFIG_VERSATILE_FPGA_IRQ) += irq-versatile-fpga.o
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obj-$(CONFIG_ARCH_NSPIRE) += irq-zevio.o

‎drivers/irqchip/irq-renesas-rzt2h.c‎

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// SPDX-License-Identifier: GPL-2.0
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#include <linux/bitfield.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/irqchip.h>
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#include <linux/irqchip/irq-renesas-rzt2h.h>
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#include <linux/irqdomain.h>
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#include <linux/of_platform.h>
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#include <linux/pm_runtime.h>
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#include <linux/reset.h>
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#include <linux/spinlock.h>
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#define RZT2H_ICU_INTCPU_NS_START 0
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#define RZT2H_ICU_INTCPU_NS_COUNT 14
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#define RZT2H_ICU_INTCPU_S_START (RZT2H_ICU_INTCPU_NS_START + \
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RZT2H_ICU_INTCPU_NS_COUNT)
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#define RZT2H_ICU_INTCPU_S_COUNT 2
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#define RZT2H_ICU_IRQ_NS_START (RZT2H_ICU_INTCPU_S_START + \
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RZT2H_ICU_INTCPU_S_COUNT)
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#define RZT2H_ICU_IRQ_NS_COUNT 14
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#define RZT2H_ICU_IRQ_S_START (RZT2H_ICU_IRQ_NS_START + \
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RZT2H_ICU_IRQ_NS_COUNT)
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#define RZT2H_ICU_IRQ_S_COUNT 2
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#define RZT2H_ICU_SEI_START (RZT2H_ICU_IRQ_S_START + \
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RZT2H_ICU_IRQ_S_COUNT)
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#define RZT2H_ICU_SEI_COUNT 1
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#define RZT2H_ICU_NUM_IRQ (RZT2H_ICU_INTCPU_NS_COUNT + \
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RZT2H_ICU_INTCPU_S_COUNT + \
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RZT2H_ICU_IRQ_NS_COUNT + \
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RZT2H_ICU_IRQ_S_COUNT + \
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RZT2H_ICU_SEI_COUNT)
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#define RZT2H_ICU_IRQ_IN_RANGE(n, type) \
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((n) >= RZT2H_ICU_##type##_START && \
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(n) < RZT2H_ICU_##type##_START + RZT2H_ICU_##type##_COUNT)
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#define RZT2H_ICU_PORTNF_MD 0xc
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#define RZT2H_ICU_PORTNF_MDi_MASK(i) (GENMASK(1, 0) << ((i) * 2))
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#define RZT2H_ICU_PORTNF_MDi_PREP(i, val) (FIELD_PREP(GENMASK(1, 0), val) << ((i) * 2))
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#define RZT2H_ICU_MD_LOW_LEVEL 0b00
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#define RZT2H_ICU_MD_FALLING_EDGE 0b01
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#define RZT2H_ICU_MD_RISING_EDGE 0b10
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#define RZT2H_ICU_MD_BOTH_EDGES 0b11
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#define RZT2H_ICU_DMACn_RSSELi(n, i) (0x7d0 + 0x18 * (n) + 0x4 * (i))
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#define RZT2H_ICU_DMAC_REQ_SELx_MASK(x) (GENMASK(9, 0) << ((x) * 10))
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#define RZT2H_ICU_DMAC_REQ_SELx_PREP(x, val) (FIELD_PREP(GENMASK(9, 0), val) << ((x) * 10))
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struct rzt2h_icu_priv {
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void __iomem *base_ns;
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void __iomem *base_s;
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struct irq_fwspec fwspec[RZT2H_ICU_NUM_IRQ];
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raw_spinlock_t lock;
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};
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void rzt2h_icu_register_dma_req(struct platform_device *icu_dev, u8 dmac_index, u8 dmac_channel,
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u16 req_no)
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{
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struct rzt2h_icu_priv *priv = platform_get_drvdata(icu_dev);
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u8 y, upper;
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u32 val;
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y = dmac_channel / 3;
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upper = dmac_channel % 3;
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guard(raw_spinlock_irqsave)(&priv->lock);
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val = readl(priv->base_ns + RZT2H_ICU_DMACn_RSSELi(dmac_index, y));
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val &= ~RZT2H_ICU_DMAC_REQ_SELx_MASK(upper);
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val |= RZT2H_ICU_DMAC_REQ_SELx_PREP(upper, req_no);
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writel(val, priv->base_ns + RZT2H_ICU_DMACn_RSSELi(dmac_index, y));
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}
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EXPORT_SYMBOL_GPL(rzt2h_icu_register_dma_req);
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static inline struct rzt2h_icu_priv *irq_data_to_priv(struct irq_data *data)
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{
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return data->domain->host_data;
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}
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static inline int rzt2h_icu_irq_to_offset(struct irq_data *d, void __iomem **base,
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unsigned int *offset)
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{
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struct rzt2h_icu_priv *priv = irq_data_to_priv(d);
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unsigned int hwirq = irqd_to_hwirq(d);
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/*
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* Safety IRQs and SEI use a separate register space from the non-safety IRQs.
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* SEI interrupt number follows immediately after the safety IRQs.
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*/
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if (RZT2H_ICU_IRQ_IN_RANGE(hwirq, IRQ_NS)) {
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*offset = hwirq - RZT2H_ICU_IRQ_NS_START;
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*base = priv->base_ns;
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} else if (RZT2H_ICU_IRQ_IN_RANGE(hwirq, IRQ_S) || RZT2H_ICU_IRQ_IN_RANGE(hwirq, SEI)) {
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*offset = hwirq - RZT2H_ICU_IRQ_S_START;
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*base = priv->base_s;
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} else {
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return -EINVAL;
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}
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return 0;
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}
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static int rzt2h_icu_irq_set_type(struct irq_data *d, unsigned int type)
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{
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struct rzt2h_icu_priv *priv = irq_data_to_priv(d);
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unsigned int offset, parent_type;
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void __iomem *base;
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u32 val, md;
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int ret;
115+
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ret = rzt2h_icu_irq_to_offset(d, &base, &offset);
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if (ret)
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return ret;
119+
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switch (type & IRQ_TYPE_SENSE_MASK) {
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case IRQ_TYPE_LEVEL_LOW:
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md = RZT2H_ICU_MD_LOW_LEVEL;
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parent_type = IRQ_TYPE_LEVEL_HIGH;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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md = RZT2H_ICU_MD_FALLING_EDGE;
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parent_type = IRQ_TYPE_EDGE_RISING;
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break;
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case IRQ_TYPE_EDGE_RISING:
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md = RZT2H_ICU_MD_RISING_EDGE;
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parent_type = IRQ_TYPE_EDGE_RISING;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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md = RZT2H_ICU_MD_BOTH_EDGES;
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parent_type = IRQ_TYPE_EDGE_RISING;
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break;
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default:
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return -EINVAL;
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}
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scoped_guard(raw_spinlock, &priv->lock) {
142+
val = readl_relaxed(base + RZT2H_ICU_PORTNF_MD);
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val &= ~RZT2H_ICU_PORTNF_MDi_MASK(offset);
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val |= RZT2H_ICU_PORTNF_MDi_PREP(offset, md);
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writel_relaxed(val, base + RZT2H_ICU_PORTNF_MD);
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}
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return irq_chip_set_type_parent(d, parent_type);
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}
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static int rzt2h_icu_set_type(struct irq_data *d, unsigned int type)
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{
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unsigned int hw_irq = irqd_to_hwirq(d);
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/* IRQn and SEI are selectable, others are edge-only. */
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if (RZT2H_ICU_IRQ_IN_RANGE(hw_irq, IRQ_NS) ||
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RZT2H_ICU_IRQ_IN_RANGE(hw_irq, IRQ_S) ||
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RZT2H_ICU_IRQ_IN_RANGE(hw_irq, SEI))
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return rzt2h_icu_irq_set_type(d, type);
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if ((type & IRQ_TYPE_SENSE_MASK) != IRQ_TYPE_EDGE_RISING)
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return -EINVAL;
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return irq_chip_set_type_parent(d, IRQ_TYPE_EDGE_RISING);
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}
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static const struct irq_chip rzt2h_icu_chip = {
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.name = "rzt2h-icu",
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.irq_mask = irq_chip_mask_parent,
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.irq_unmask = irq_chip_unmask_parent,
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.irq_eoi = irq_chip_eoi_parent,
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.irq_set_type = rzt2h_icu_set_type,
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.irq_set_wake = irq_chip_set_wake_parent,
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.irq_set_affinity = irq_chip_set_affinity_parent,
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.irq_retrigger = irq_chip_retrigger_hierarchy,
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.irq_get_irqchip_state = irq_chip_get_parent_state,
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.irq_set_irqchip_state = irq_chip_set_parent_state,
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.flags = IRQCHIP_MASK_ON_SUSPEND |
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IRQCHIP_SET_TYPE_MASKED |
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IRQCHIP_SKIP_SET_WAKE,
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};
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static int rzt2h_icu_alloc(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs,
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void *arg)
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{
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struct rzt2h_icu_priv *priv = domain->host_data;
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irq_hw_number_t hwirq;
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unsigned int type;
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int ret;
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ret = irq_domain_translate_twocell(domain, arg, &hwirq, &type);
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if (ret)
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return ret;
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ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, &rzt2h_icu_chip, NULL);
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if (ret)
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return ret;
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return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &priv->fwspec[hwirq]);
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}
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static const struct irq_domain_ops rzt2h_icu_domain_ops = {
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.alloc = rzt2h_icu_alloc,
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.free = irq_domain_free_irqs_common,
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.translate = irq_domain_translate_twocell,
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};
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static int rzt2h_icu_parse_interrupts(struct rzt2h_icu_priv *priv, struct device_node *np)
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{
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struct of_phandle_args map;
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unsigned int i;
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int ret;
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for (i = 0; i < RZT2H_ICU_NUM_IRQ; i++) {
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ret = of_irq_parse_one(np, i, &map);
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if (ret)
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return ret;
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of_phandle_args_to_fwspec(np, map.args, map.args_count, &priv->fwspec[i]);
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}
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return 0;
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}
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static int rzt2h_icu_init(struct platform_device *pdev, struct device_node *parent)
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{
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struct irq_domain *irq_domain, *parent_domain;
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struct device_node *node = pdev->dev.of_node;
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struct device *dev = &pdev->dev;
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struct rzt2h_icu_priv *priv;
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int ret;
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parent_domain = irq_find_host(parent);
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if (!parent_domain)
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return dev_err_probe(dev, -ENODEV, "cannot find parent domain\n");
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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raw_spin_lock_init(&priv->lock);
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platform_set_drvdata(pdev, priv);
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priv->base_ns = devm_of_iomap(dev, dev->of_node, 0, NULL);
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if (IS_ERR(priv->base_ns))
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return PTR_ERR(priv->base_ns);
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priv->base_s = devm_of_iomap(dev, dev->of_node, 1, NULL);
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if (IS_ERR(priv->base_s))
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return PTR_ERR(priv->base_s);
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ret = rzt2h_icu_parse_interrupts(priv, node);
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if (ret)
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return dev_err_probe(dev, ret, "cannot parse interrupts: %d\n", ret);
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ret = devm_pm_runtime_enable(dev);
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if (ret)
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return dev_err_probe(dev, ret, "devm_pm_runtime_enable failed: %d\n", ret);
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ret = pm_runtime_resume_and_get(dev);
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if (ret)
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return dev_err_probe(dev, ret, "pm_runtime_resume_and_get failed: %d\n", ret);
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irq_domain = irq_domain_create_hierarchy(parent_domain, 0, RZT2H_ICU_NUM_IRQ,
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dev_fwnode(dev), &rzt2h_icu_domain_ops, priv);
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if (!irq_domain) {
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pm_runtime_put(dev);
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return -ENOMEM;
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}
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return 0;
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}
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IRQCHIP_PLATFORM_DRIVER_BEGIN(rzt2h_icu)
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IRQCHIP_MATCH("renesas,r9a09g077-icu", rzt2h_icu_init)
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IRQCHIP_PLATFORM_DRIVER_END(rzt2h_icu)
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MODULE_AUTHOR("Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>");
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MODULE_DESCRIPTION("Renesas RZ/T2H ICU Driver");
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MODULE_LICENSE("GPL");

‎drivers/soc/renesas/Kconfig‎

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Original file line numberDiff line numberDiff line change
@@ -423,6 +423,7 @@ config ARCH_R9A09G057
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config ARCH_R9A09G077
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bool "ARM64 Platform support for R9A09G077 (RZ/T2H)"
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default y if ARCH_RENESAS
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select RENESAS_RZT2H_ICU
426427
help
427428
This enables support for the Renesas RZ/T2H SoC variants.
428429

‎include/linux/irqchip/irq-renesas-rzt2h.h‎

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@@ -0,0 +1,23 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Renesas RZ/T2H Interrupt Control Unit (ICU)
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*
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* Copyright (C) 2025 Renesas Electronics Corporation.
6+
*/
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#ifndef __LINUX_IRQ_RENESAS_RZT2H
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#define __LINUX_IRQ_RENESAS_RZT2H
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#include <linux/platform_device.h>
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#define RZT2H_ICU_DMAC_REQ_NO_DEFAULT 0x3ff
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#ifdef CONFIG_RENESAS_RZT2H_ICU
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void rzt2h_icu_register_dma_req(struct platform_device *icu_dev, u8 dmac_index, u8 dmac_channel,
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u16 req_no);
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#else
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static inline void rzt2h_icu_register_dma_req(struct platform_device *icu_dev, u8 dmac_index,
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u8 dmac_channel, u16 req_no) { }
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#endif
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#endif /* __LINUX_IRQ_RENESAS_RZT2H */

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