Skip to content

Commit 141fbc2

Browse files
superna9999jbrun3t
superna9999
authored and
jbrun3t
committed
clk: meson: migrate meson-eeclk out of hw_onecell_data to drop NR_CLKS
The way hw_onecell_data is declared: struct clk_hw_onecell_data { unsigned int num; struct clk_hw *hws[]; }; makes it impossible to have the clk_hw table declared outside while using ARRAY_SIZE() to determine ".num" due to ".hws" being a flexible array member. Completely move out of hw_onecell_data and add a custom devm_of_clk_add_hw_provider() "get" callback to retrieve the clk_hw from the meson_eeclkc_data struct to finally get rid on the NR_CLKS define. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-2-38172d17c27a@linaro.org Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
1 parent 230b6f3 commit 141fbc2

9 files changed

Lines changed: 1312 additions & 1323 deletions

File tree

‎drivers/clk/meson/Kconfig‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -41,6 +41,7 @@ config COMMON_CLK_MESON_AO_CLKC
4141
config COMMON_CLK_MESON_EE_CLKC
4242
tristate
4343
select COMMON_CLK_MESON_REGMAP
44+
select COMMON_CLK_MESON_CLKC_UTILS
4445

4546
config COMMON_CLK_MESON_CPU_DYNDIV
4647
tristate

‎drivers/clk/meson/axg.c‎

Lines changed: 141 additions & 142 deletions
Original file line numberDiff line numberDiff line change
@@ -1890,147 +1890,143 @@ static MESON_GATE(axg_ao_i2c, HHI_GCLK_AO, 4);
18901890

18911891
/* Array of all clocks provided by this provider */
18921892

1893-
static struct clk_hw_onecell_data axg_hw_onecell_data = {
1894-
.hws = {
1895-
[CLKID_SYS_PLL] = &axg_sys_pll.hw,
1896-
[CLKID_FIXED_PLL] = &axg_fixed_pll.hw,
1897-
[CLKID_FCLK_DIV2] = &axg_fclk_div2.hw,
1898-
[CLKID_FCLK_DIV3] = &axg_fclk_div3.hw,
1899-
[CLKID_FCLK_DIV4] = &axg_fclk_div4.hw,
1900-
[CLKID_FCLK_DIV5] = &axg_fclk_div5.hw,
1901-
[CLKID_FCLK_DIV7] = &axg_fclk_div7.hw,
1902-
[CLKID_GP0_PLL] = &axg_gp0_pll.hw,
1903-
[CLKID_MPEG_SEL] = &axg_mpeg_clk_sel.hw,
1904-
[CLKID_MPEG_DIV] = &axg_mpeg_clk_div.hw,
1905-
[CLKID_CLK81] = &axg_clk81.hw,
1906-
[CLKID_MPLL0] = &axg_mpll0.hw,
1907-
[CLKID_MPLL1] = &axg_mpll1.hw,
1908-
[CLKID_MPLL2] = &axg_mpll2.hw,
1909-
[CLKID_MPLL3] = &axg_mpll3.hw,
1910-
[CLKID_DDR] = &axg_ddr.hw,
1911-
[CLKID_AUDIO_LOCKER] = &axg_audio_locker.hw,
1912-
[CLKID_MIPI_DSI_HOST] = &axg_mipi_dsi_host.hw,
1913-
[CLKID_ISA] = &axg_isa.hw,
1914-
[CLKID_PL301] = &axg_pl301.hw,
1915-
[CLKID_PERIPHS] = &axg_periphs.hw,
1916-
[CLKID_SPICC0] = &axg_spicc_0.hw,
1917-
[CLKID_I2C] = &axg_i2c.hw,
1918-
[CLKID_RNG0] = &axg_rng0.hw,
1919-
[CLKID_UART0] = &axg_uart0.hw,
1920-
[CLKID_MIPI_DSI_PHY] = &axg_mipi_dsi_phy.hw,
1921-
[CLKID_SPICC1] = &axg_spicc_1.hw,
1922-
[CLKID_PCIE_A] = &axg_pcie_a.hw,
1923-
[CLKID_PCIE_B] = &axg_pcie_b.hw,
1924-
[CLKID_HIU_IFACE] = &axg_hiu_reg.hw,
1925-
[CLKID_ASSIST_MISC] = &axg_assist_misc.hw,
1926-
[CLKID_SD_EMMC_B] = &axg_emmc_b.hw,
1927-
[CLKID_SD_EMMC_C] = &axg_emmc_c.hw,
1928-
[CLKID_DMA] = &axg_dma.hw,
1929-
[CLKID_SPI] = &axg_spi.hw,
1930-
[CLKID_AUDIO] = &axg_audio.hw,
1931-
[CLKID_ETH] = &axg_eth_core.hw,
1932-
[CLKID_UART1] = &axg_uart1.hw,
1933-
[CLKID_G2D] = &axg_g2d.hw,
1934-
[CLKID_USB0] = &axg_usb0.hw,
1935-
[CLKID_USB1] = &axg_usb1.hw,
1936-
[CLKID_RESET] = &axg_reset.hw,
1937-
[CLKID_USB] = &axg_usb_general.hw,
1938-
[CLKID_AHB_ARB0] = &axg_ahb_arb0.hw,
1939-
[CLKID_EFUSE] = &axg_efuse.hw,
1940-
[CLKID_BOOT_ROM] = &axg_boot_rom.hw,
1941-
[CLKID_AHB_DATA_BUS] = &axg_ahb_data_bus.hw,
1942-
[CLKID_AHB_CTRL_BUS] = &axg_ahb_ctrl_bus.hw,
1943-
[CLKID_USB1_DDR_BRIDGE] = &axg_usb1_to_ddr.hw,
1944-
[CLKID_USB0_DDR_BRIDGE] = &axg_usb0_to_ddr.hw,
1945-
[CLKID_MMC_PCLK] = &axg_mmc_pclk.hw,
1946-
[CLKID_VPU_INTR] = &axg_vpu_intr.hw,
1947-
[CLKID_SEC_AHB_AHB3_BRIDGE] = &axg_sec_ahb_ahb3_bridge.hw,
1948-
[CLKID_GIC] = &axg_gic.hw,
1949-
[CLKID_AO_MEDIA_CPU] = &axg_ao_media_cpu.hw,
1950-
[CLKID_AO_AHB_SRAM] = &axg_ao_ahb_sram.hw,
1951-
[CLKID_AO_AHB_BUS] = &axg_ao_ahb_bus.hw,
1952-
[CLKID_AO_IFACE] = &axg_ao_iface.hw,
1953-
[CLKID_AO_I2C] = &axg_ao_i2c.hw,
1954-
[CLKID_SD_EMMC_B_CLK0_SEL] = &axg_sd_emmc_b_clk0_sel.hw,
1955-
[CLKID_SD_EMMC_B_CLK0_DIV] = &axg_sd_emmc_b_clk0_div.hw,
1956-
[CLKID_SD_EMMC_B_CLK0] = &axg_sd_emmc_b_clk0.hw,
1957-
[CLKID_SD_EMMC_C_CLK0_SEL] = &axg_sd_emmc_c_clk0_sel.hw,
1958-
[CLKID_SD_EMMC_C_CLK0_DIV] = &axg_sd_emmc_c_clk0_div.hw,
1959-
[CLKID_SD_EMMC_C_CLK0] = &axg_sd_emmc_c_clk0.hw,
1960-
[CLKID_MPLL0_DIV] = &axg_mpll0_div.hw,
1961-
[CLKID_MPLL1_DIV] = &axg_mpll1_div.hw,
1962-
[CLKID_MPLL2_DIV] = &axg_mpll2_div.hw,
1963-
[CLKID_MPLL3_DIV] = &axg_mpll3_div.hw,
1964-
[CLKID_HIFI_PLL] = &axg_hifi_pll.hw,
1965-
[CLKID_MPLL_PREDIV] = &axg_mpll_prediv.hw,
1966-
[CLKID_FCLK_DIV2_DIV] = &axg_fclk_div2_div.hw,
1967-
[CLKID_FCLK_DIV3_DIV] = &axg_fclk_div3_div.hw,
1968-
[CLKID_FCLK_DIV4_DIV] = &axg_fclk_div4_div.hw,
1969-
[CLKID_FCLK_DIV5_DIV] = &axg_fclk_div5_div.hw,
1970-
[CLKID_FCLK_DIV7_DIV] = &axg_fclk_div7_div.hw,
1971-
[CLKID_PCIE_PLL] = &axg_pcie_pll.hw,
1972-
[CLKID_PCIE_MUX] = &axg_pcie_mux.hw,
1973-
[CLKID_PCIE_REF] = &axg_pcie_ref.hw,
1974-
[CLKID_PCIE_CML_EN0] = &axg_pcie_cml_en0.hw,
1975-
[CLKID_PCIE_CML_EN1] = &axg_pcie_cml_en1.hw,
1976-
[CLKID_GEN_CLK_SEL] = &axg_gen_clk_sel.hw,
1977-
[CLKID_GEN_CLK_DIV] = &axg_gen_clk_div.hw,
1978-
[CLKID_GEN_CLK] = &axg_gen_clk.hw,
1979-
[CLKID_SYS_PLL_DCO] = &axg_sys_pll_dco.hw,
1980-
[CLKID_FIXED_PLL_DCO] = &axg_fixed_pll_dco.hw,
1981-
[CLKID_GP0_PLL_DCO] = &axg_gp0_pll_dco.hw,
1982-
[CLKID_HIFI_PLL_DCO] = &axg_hifi_pll_dco.hw,
1983-
[CLKID_PCIE_PLL_DCO] = &axg_pcie_pll_dco.hw,
1984-
[CLKID_PCIE_PLL_OD] = &axg_pcie_pll_od.hw,
1985-
[CLKID_VPU_0_DIV] = &axg_vpu_0_div.hw,
1986-
[CLKID_VPU_0_SEL] = &axg_vpu_0_sel.hw,
1987-
[CLKID_VPU_0] = &axg_vpu_0.hw,
1988-
[CLKID_VPU_1_DIV] = &axg_vpu_1_div.hw,
1989-
[CLKID_VPU_1_SEL] = &axg_vpu_1_sel.hw,
1990-
[CLKID_VPU_1] = &axg_vpu_1.hw,
1991-
[CLKID_VPU] = &axg_vpu.hw,
1992-
[CLKID_VAPB_0_DIV] = &axg_vapb_0_div.hw,
1993-
[CLKID_VAPB_0_SEL] = &axg_vapb_0_sel.hw,
1994-
[CLKID_VAPB_0] = &axg_vapb_0.hw,
1995-
[CLKID_VAPB_1_DIV] = &axg_vapb_1_div.hw,
1996-
[CLKID_VAPB_1_SEL] = &axg_vapb_1_sel.hw,
1997-
[CLKID_VAPB_1] = &axg_vapb_1.hw,
1998-
[CLKID_VAPB_SEL] = &axg_vapb_sel.hw,
1999-
[CLKID_VAPB] = &axg_vapb.hw,
2000-
[CLKID_VCLK] = &axg_vclk.hw,
2001-
[CLKID_VCLK2] = &axg_vclk2.hw,
2002-
[CLKID_VCLK_SEL] = &axg_vclk_sel.hw,
2003-
[CLKID_VCLK2_SEL] = &axg_vclk2_sel.hw,
2004-
[CLKID_VCLK_INPUT] = &axg_vclk_input.hw,
2005-
[CLKID_VCLK2_INPUT] = &axg_vclk2_input.hw,
2006-
[CLKID_VCLK_DIV] = &axg_vclk_div.hw,
2007-
[CLKID_VCLK2_DIV] = &axg_vclk2_div.hw,
2008-
[CLKID_VCLK_DIV2_EN] = &axg_vclk_div2_en.hw,
2009-
[CLKID_VCLK_DIV4_EN] = &axg_vclk_div4_en.hw,
2010-
[CLKID_VCLK_DIV6_EN] = &axg_vclk_div6_en.hw,
2011-
[CLKID_VCLK_DIV12_EN] = &axg_vclk_div12_en.hw,
2012-
[CLKID_VCLK2_DIV2_EN] = &axg_vclk2_div2_en.hw,
2013-
[CLKID_VCLK2_DIV4_EN] = &axg_vclk2_div4_en.hw,
2014-
[CLKID_VCLK2_DIV6_EN] = &axg_vclk2_div6_en.hw,
2015-
[CLKID_VCLK2_DIV12_EN] = &axg_vclk2_div12_en.hw,
2016-
[CLKID_VCLK_DIV1] = &axg_vclk_div1.hw,
2017-
[CLKID_VCLK_DIV2] = &axg_vclk_div2.hw,
2018-
[CLKID_VCLK_DIV4] = &axg_vclk_div4.hw,
2019-
[CLKID_VCLK_DIV6] = &axg_vclk_div6.hw,
2020-
[CLKID_VCLK_DIV12] = &axg_vclk_div12.hw,
2021-
[CLKID_VCLK2_DIV1] = &axg_vclk2_div1.hw,
2022-
[CLKID_VCLK2_DIV2] = &axg_vclk2_div2.hw,
2023-
[CLKID_VCLK2_DIV4] = &axg_vclk2_div4.hw,
2024-
[CLKID_VCLK2_DIV6] = &axg_vclk2_div6.hw,
2025-
[CLKID_VCLK2_DIV12] = &axg_vclk2_div12.hw,
2026-
[CLKID_CTS_ENCL_SEL] = &axg_cts_encl_sel.hw,
2027-
[CLKID_CTS_ENCL] = &axg_cts_encl.hw,
2028-
[CLKID_VDIN_MEAS_SEL] = &axg_vdin_meas_sel.hw,
2029-
[CLKID_VDIN_MEAS_DIV] = &axg_vdin_meas_div.hw,
2030-
[CLKID_VDIN_MEAS] = &axg_vdin_meas.hw,
2031-
[NR_CLKS] = NULL,
2032-
},
2033-
.num = NR_CLKS,
1893+
static struct clk_hw *axg_hw_clks[] = {
1894+
[CLKID_SYS_PLL] = &axg_sys_pll.hw,
1895+
[CLKID_FIXED_PLL] = &axg_fixed_pll.hw,
1896+
[CLKID_FCLK_DIV2] = &axg_fclk_div2.hw,
1897+
[CLKID_FCLK_DIV3] = &axg_fclk_div3.hw,
1898+
[CLKID_FCLK_DIV4] = &axg_fclk_div4.hw,
1899+
[CLKID_FCLK_DIV5] = &axg_fclk_div5.hw,
1900+
[CLKID_FCLK_DIV7] = &axg_fclk_div7.hw,
1901+
[CLKID_GP0_PLL] = &axg_gp0_pll.hw,
1902+
[CLKID_MPEG_SEL] = &axg_mpeg_clk_sel.hw,
1903+
[CLKID_MPEG_DIV] = &axg_mpeg_clk_div.hw,
1904+
[CLKID_CLK81] = &axg_clk81.hw,
1905+
[CLKID_MPLL0] = &axg_mpll0.hw,
1906+
[CLKID_MPLL1] = &axg_mpll1.hw,
1907+
[CLKID_MPLL2] = &axg_mpll2.hw,
1908+
[CLKID_MPLL3] = &axg_mpll3.hw,
1909+
[CLKID_DDR] = &axg_ddr.hw,
1910+
[CLKID_AUDIO_LOCKER] = &axg_audio_locker.hw,
1911+
[CLKID_MIPI_DSI_HOST] = &axg_mipi_dsi_host.hw,
1912+
[CLKID_ISA] = &axg_isa.hw,
1913+
[CLKID_PL301] = &axg_pl301.hw,
1914+
[CLKID_PERIPHS] = &axg_periphs.hw,
1915+
[CLKID_SPICC0] = &axg_spicc_0.hw,
1916+
[CLKID_I2C] = &axg_i2c.hw,
1917+
[CLKID_RNG0] = &axg_rng0.hw,
1918+
[CLKID_UART0] = &axg_uart0.hw,
1919+
[CLKID_MIPI_DSI_PHY] = &axg_mipi_dsi_phy.hw,
1920+
[CLKID_SPICC1] = &axg_spicc_1.hw,
1921+
[CLKID_PCIE_A] = &axg_pcie_a.hw,
1922+
[CLKID_PCIE_B] = &axg_pcie_b.hw,
1923+
[CLKID_HIU_IFACE] = &axg_hiu_reg.hw,
1924+
[CLKID_ASSIST_MISC] = &axg_assist_misc.hw,
1925+
[CLKID_SD_EMMC_B] = &axg_emmc_b.hw,
1926+
[CLKID_SD_EMMC_C] = &axg_emmc_c.hw,
1927+
[CLKID_DMA] = &axg_dma.hw,
1928+
[CLKID_SPI] = &axg_spi.hw,
1929+
[CLKID_AUDIO] = &axg_audio.hw,
1930+
[CLKID_ETH] = &axg_eth_core.hw,
1931+
[CLKID_UART1] = &axg_uart1.hw,
1932+
[CLKID_G2D] = &axg_g2d.hw,
1933+
[CLKID_USB0] = &axg_usb0.hw,
1934+
[CLKID_USB1] = &axg_usb1.hw,
1935+
[CLKID_RESET] = &axg_reset.hw,
1936+
[CLKID_USB] = &axg_usb_general.hw,
1937+
[CLKID_AHB_ARB0] = &axg_ahb_arb0.hw,
1938+
[CLKID_EFUSE] = &axg_efuse.hw,
1939+
[CLKID_BOOT_ROM] = &axg_boot_rom.hw,
1940+
[CLKID_AHB_DATA_BUS] = &axg_ahb_data_bus.hw,
1941+
[CLKID_AHB_CTRL_BUS] = &axg_ahb_ctrl_bus.hw,
1942+
[CLKID_USB1_DDR_BRIDGE] = &axg_usb1_to_ddr.hw,
1943+
[CLKID_USB0_DDR_BRIDGE] = &axg_usb0_to_ddr.hw,
1944+
[CLKID_MMC_PCLK] = &axg_mmc_pclk.hw,
1945+
[CLKID_VPU_INTR] = &axg_vpu_intr.hw,
1946+
[CLKID_SEC_AHB_AHB3_BRIDGE] = &axg_sec_ahb_ahb3_bridge.hw,
1947+
[CLKID_GIC] = &axg_gic.hw,
1948+
[CLKID_AO_MEDIA_CPU] = &axg_ao_media_cpu.hw,
1949+
[CLKID_AO_AHB_SRAM] = &axg_ao_ahb_sram.hw,
1950+
[CLKID_AO_AHB_BUS] = &axg_ao_ahb_bus.hw,
1951+
[CLKID_AO_IFACE] = &axg_ao_iface.hw,
1952+
[CLKID_AO_I2C] = &axg_ao_i2c.hw,
1953+
[CLKID_SD_EMMC_B_CLK0_SEL] = &axg_sd_emmc_b_clk0_sel.hw,
1954+
[CLKID_SD_EMMC_B_CLK0_DIV] = &axg_sd_emmc_b_clk0_div.hw,
1955+
[CLKID_SD_EMMC_B_CLK0] = &axg_sd_emmc_b_clk0.hw,
1956+
[CLKID_SD_EMMC_C_CLK0_SEL] = &axg_sd_emmc_c_clk0_sel.hw,
1957+
[CLKID_SD_EMMC_C_CLK0_DIV] = &axg_sd_emmc_c_clk0_div.hw,
1958+
[CLKID_SD_EMMC_C_CLK0] = &axg_sd_emmc_c_clk0.hw,
1959+
[CLKID_MPLL0_DIV] = &axg_mpll0_div.hw,
1960+
[CLKID_MPLL1_DIV] = &axg_mpll1_div.hw,
1961+
[CLKID_MPLL2_DIV] = &axg_mpll2_div.hw,
1962+
[CLKID_MPLL3_DIV] = &axg_mpll3_div.hw,
1963+
[CLKID_HIFI_PLL] = &axg_hifi_pll.hw,
1964+
[CLKID_MPLL_PREDIV] = &axg_mpll_prediv.hw,
1965+
[CLKID_FCLK_DIV2_DIV] = &axg_fclk_div2_div.hw,
1966+
[CLKID_FCLK_DIV3_DIV] = &axg_fclk_div3_div.hw,
1967+
[CLKID_FCLK_DIV4_DIV] = &axg_fclk_div4_div.hw,
1968+
[CLKID_FCLK_DIV5_DIV] = &axg_fclk_div5_div.hw,
1969+
[CLKID_FCLK_DIV7_DIV] = &axg_fclk_div7_div.hw,
1970+
[CLKID_PCIE_PLL] = &axg_pcie_pll.hw,
1971+
[CLKID_PCIE_MUX] = &axg_pcie_mux.hw,
1972+
[CLKID_PCIE_REF] = &axg_pcie_ref.hw,
1973+
[CLKID_PCIE_CML_EN0] = &axg_pcie_cml_en0.hw,
1974+
[CLKID_PCIE_CML_EN1] = &axg_pcie_cml_en1.hw,
1975+
[CLKID_GEN_CLK_SEL] = &axg_gen_clk_sel.hw,
1976+
[CLKID_GEN_CLK_DIV] = &axg_gen_clk_div.hw,
1977+
[CLKID_GEN_CLK] = &axg_gen_clk.hw,
1978+
[CLKID_SYS_PLL_DCO] = &axg_sys_pll_dco.hw,
1979+
[CLKID_FIXED_PLL_DCO] = &axg_fixed_pll_dco.hw,
1980+
[CLKID_GP0_PLL_DCO] = &axg_gp0_pll_dco.hw,
1981+
[CLKID_HIFI_PLL_DCO] = &axg_hifi_pll_dco.hw,
1982+
[CLKID_PCIE_PLL_DCO] = &axg_pcie_pll_dco.hw,
1983+
[CLKID_PCIE_PLL_OD] = &axg_pcie_pll_od.hw,
1984+
[CLKID_VPU_0_DIV] = &axg_vpu_0_div.hw,
1985+
[CLKID_VPU_0_SEL] = &axg_vpu_0_sel.hw,
1986+
[CLKID_VPU_0] = &axg_vpu_0.hw,
1987+
[CLKID_VPU_1_DIV] = &axg_vpu_1_div.hw,
1988+
[CLKID_VPU_1_SEL] = &axg_vpu_1_sel.hw,
1989+
[CLKID_VPU_1] = &axg_vpu_1.hw,
1990+
[CLKID_VPU] = &axg_vpu.hw,
1991+
[CLKID_VAPB_0_DIV] = &axg_vapb_0_div.hw,
1992+
[CLKID_VAPB_0_SEL] = &axg_vapb_0_sel.hw,
1993+
[CLKID_VAPB_0] = &axg_vapb_0.hw,
1994+
[CLKID_VAPB_1_DIV] = &axg_vapb_1_div.hw,
1995+
[CLKID_VAPB_1_SEL] = &axg_vapb_1_sel.hw,
1996+
[CLKID_VAPB_1] = &axg_vapb_1.hw,
1997+
[CLKID_VAPB_SEL] = &axg_vapb_sel.hw,
1998+
[CLKID_VAPB] = &axg_vapb.hw,
1999+
[CLKID_VCLK] = &axg_vclk.hw,
2000+
[CLKID_VCLK2] = &axg_vclk2.hw,
2001+
[CLKID_VCLK_SEL] = &axg_vclk_sel.hw,
2002+
[CLKID_VCLK2_SEL] = &axg_vclk2_sel.hw,
2003+
[CLKID_VCLK_INPUT] = &axg_vclk_input.hw,
2004+
[CLKID_VCLK2_INPUT] = &axg_vclk2_input.hw,
2005+
[CLKID_VCLK_DIV] = &axg_vclk_div.hw,
2006+
[CLKID_VCLK2_DIV] = &axg_vclk2_div.hw,
2007+
[CLKID_VCLK_DIV2_EN] = &axg_vclk_div2_en.hw,
2008+
[CLKID_VCLK_DIV4_EN] = &axg_vclk_div4_en.hw,
2009+
[CLKID_VCLK_DIV6_EN] = &axg_vclk_div6_en.hw,
2010+
[CLKID_VCLK_DIV12_EN] = &axg_vclk_div12_en.hw,
2011+
[CLKID_VCLK2_DIV2_EN] = &axg_vclk2_div2_en.hw,
2012+
[CLKID_VCLK2_DIV4_EN] = &axg_vclk2_div4_en.hw,
2013+
[CLKID_VCLK2_DIV6_EN] = &axg_vclk2_div6_en.hw,
2014+
[CLKID_VCLK2_DIV12_EN] = &axg_vclk2_div12_en.hw,
2015+
[CLKID_VCLK_DIV1] = &axg_vclk_div1.hw,
2016+
[CLKID_VCLK_DIV2] = &axg_vclk_div2.hw,
2017+
[CLKID_VCLK_DIV4] = &axg_vclk_div4.hw,
2018+
[CLKID_VCLK_DIV6] = &axg_vclk_div6.hw,
2019+
[CLKID_VCLK_DIV12] = &axg_vclk_div12.hw,
2020+
[CLKID_VCLK2_DIV1] = &axg_vclk2_div1.hw,
2021+
[CLKID_VCLK2_DIV2] = &axg_vclk2_div2.hw,
2022+
[CLKID_VCLK2_DIV4] = &axg_vclk2_div4.hw,
2023+
[CLKID_VCLK2_DIV6] = &axg_vclk2_div6.hw,
2024+
[CLKID_VCLK2_DIV12] = &axg_vclk2_div12.hw,
2025+
[CLKID_CTS_ENCL_SEL] = &axg_cts_encl_sel.hw,
2026+
[CLKID_CTS_ENCL] = &axg_cts_encl.hw,
2027+
[CLKID_VDIN_MEAS_SEL] = &axg_vdin_meas_sel.hw,
2028+
[CLKID_VDIN_MEAS_DIV] = &axg_vdin_meas_div.hw,
2029+
[CLKID_VDIN_MEAS] = &axg_vdin_meas.hw,
20342030
};
20352031

20362032
/* Convenience table to populate regmap in .probe */
@@ -2163,7 +2159,10 @@ static struct clk_regmap *const axg_clk_regmaps[] = {
21632159
static const struct meson_eeclkc_data axg_clkc_data = {
21642160
.regmap_clks = axg_clk_regmaps,
21652161
.regmap_clk_num = ARRAY_SIZE(axg_clk_regmaps),
2166-
.hw_onecell_data = &axg_hw_onecell_data,
2162+
.hw_clks = {
2163+
.hws = axg_hw_clks,
2164+
.num = ARRAY_SIZE(axg_hw_clks),
2165+
},
21672166
};
21682167

21692168

‎drivers/clk/meson/axg.h‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -160,8 +160,6 @@
160160
#define CLKID_VDIN_MEAS_SEL 134
161161
#define CLKID_VDIN_MEAS_DIV 135
162162

163-
#define NR_CLKS 137
164-
165163
/* include the CLKIDs that have been made part of the DT binding */
166164
#include <dt-bindings/clock/axg-clkc.h>
167165

0 commit comments

Comments
 (0)