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bebarinobebarino
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Merge tag 'clk-meson-v6.8-1' of https://github.com/BayLibre/clk-meson into clk-amlogic
Pull Amlogic clk driver updates from Jerome Brunet: - Add DSI clocks on Amlogic g12/sm1 - Add CSI and ISP clocks on Amlogic g12/sm1 * tag 'clk-meson-v6.8-1' of https://github.com/BayLibre/clk-meson: clk: meson: g12a: add CSI & ISP gates clocks clk: meson: g12a: add MIPI ISP clocks dt-bindings: clock: g12a-clkc: add MIPI ISP & CSI PHY clock ids clk: meson: g12a: add CTS_ENCL & CTS_ENCL_SEL clocks dt-bindings: clk: g12a-clkc: add CTS_ENCL clock ids
2 parents b85ea95 + 5205628 commit 145916f

3 files changed

Lines changed: 124 additions & 0 deletions

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‎drivers/clk/meson/g12a.c‎

Lines changed: 115 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3549,6 +3549,22 @@ static struct clk_regmap g12a_cts_encp_sel = {
35493549
},
35503550
};
35513551

3552+
static struct clk_regmap g12a_cts_encl_sel = {
3553+
.data = &(struct clk_regmap_mux_data){
3554+
.offset = HHI_VIID_CLK_DIV,
3555+
.mask = 0xf,
3556+
.shift = 12,
3557+
.table = mux_table_cts_sel,
3558+
},
3559+
.hw.init = &(struct clk_init_data){
3560+
.name = "cts_encl_sel",
3561+
.ops = &clk_regmap_mux_ops,
3562+
.parent_hws = g12a_cts_parent_hws,
3563+
.num_parents = ARRAY_SIZE(g12a_cts_parent_hws),
3564+
.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
3565+
},
3566+
};
3567+
35523568
static struct clk_regmap g12a_cts_vdac_sel = {
35533569
.data = &(struct clk_regmap_mux_data){
35543570
.offset = HHI_VIID_CLK_DIV,
@@ -3628,6 +3644,22 @@ static struct clk_regmap g12a_cts_encp = {
36283644
},
36293645
};
36303646

3647+
static struct clk_regmap g12a_cts_encl = {
3648+
.data = &(struct clk_regmap_gate_data){
3649+
.offset = HHI_VID_CLK_CNTL2,
3650+
.bit_idx = 3,
3651+
},
3652+
.hw.init = &(struct clk_init_data) {
3653+
.name = "cts_encl",
3654+
.ops = &clk_regmap_gate_ops,
3655+
.parent_hws = (const struct clk_hw *[]) {
3656+
&g12a_cts_encl_sel.hw
3657+
},
3658+
.num_parents = 1,
3659+
.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3660+
},
3661+
};
3662+
36313663
static struct clk_regmap g12a_cts_vdac = {
36323664
.data = &(struct clk_regmap_gate_data){
36333665
.offset = HHI_VID_CLK_CNTL2,
@@ -3722,6 +3754,66 @@ static struct clk_regmap g12a_mipi_dsi_pxclk = {
37223754
},
37233755
};
37243756

3757+
/* MIPI ISP Clocks */
3758+
3759+
static const struct clk_parent_data g12b_mipi_isp_parent_data[] = {
3760+
{ .fw_name = "xtal", },
3761+
{ .hw = &g12a_gp0_pll.hw },
3762+
{ .hw = &g12a_hifi_pll.hw },
3763+
{ .hw = &g12a_fclk_div2p5.hw },
3764+
{ .hw = &g12a_fclk_div3.hw },
3765+
{ .hw = &g12a_fclk_div4.hw },
3766+
{ .hw = &g12a_fclk_div5.hw },
3767+
{ .hw = &g12a_fclk_div7.hw },
3768+
};
3769+
3770+
static struct clk_regmap g12b_mipi_isp_sel = {
3771+
.data = &(struct clk_regmap_mux_data){
3772+
.offset = HHI_ISP_CLK_CNTL,
3773+
.mask = 7,
3774+
.shift = 9,
3775+
},
3776+
.hw.init = &(struct clk_init_data){
3777+
.name = "mipi_isp_sel",
3778+
.ops = &clk_regmap_mux_ops,
3779+
.parent_data = g12b_mipi_isp_parent_data,
3780+
.num_parents = ARRAY_SIZE(g12b_mipi_isp_parent_data),
3781+
},
3782+
};
3783+
3784+
static struct clk_regmap g12b_mipi_isp_div = {
3785+
.data = &(struct clk_regmap_div_data){
3786+
.offset = HHI_ISP_CLK_CNTL,
3787+
.shift = 0,
3788+
.width = 7,
3789+
},
3790+
.hw.init = &(struct clk_init_data){
3791+
.name = "mipi_isp_div",
3792+
.ops = &clk_regmap_divider_ops,
3793+
.parent_hws = (const struct clk_hw *[]) {
3794+
&g12b_mipi_isp_sel.hw
3795+
},
3796+
.num_parents = 1,
3797+
.flags = CLK_SET_RATE_PARENT,
3798+
},
3799+
};
3800+
3801+
static struct clk_regmap g12b_mipi_isp = {
3802+
.data = &(struct clk_regmap_gate_data){
3803+
.offset = HHI_ISP_CLK_CNTL,
3804+
.bit_idx = 8,
3805+
},
3806+
.hw.init = &(struct clk_init_data) {
3807+
.name = "mipi_isp",
3808+
.ops = &clk_regmap_gate_ops,
3809+
.parent_hws = (const struct clk_hw *[]) {
3810+
&g12b_mipi_isp_div.hw
3811+
},
3812+
.num_parents = 1,
3813+
.flags = CLK_SET_RATE_PARENT,
3814+
},
3815+
};
3816+
37253817
/* HDMI Clocks */
37263818

37273819
static const struct clk_parent_data g12a_hdmi_parent_data[] = {
@@ -4214,9 +4306,12 @@ static MESON_GATE(g12a_htx_hdcp22, HHI_GCLK_MPEG2, 3);
42144306
static MESON_GATE(g12a_htx_pclk, HHI_GCLK_MPEG2, 4);
42154307
static MESON_GATE(g12a_bt656, HHI_GCLK_MPEG2, 6);
42164308
static MESON_GATE(g12a_usb1_to_ddr, HHI_GCLK_MPEG2, 8);
4309+
static MESON_GATE(g12b_mipi_isp_gate, HHI_GCLK_MPEG2, 17);
42174310
static MESON_GATE(g12a_mmc_pclk, HHI_GCLK_MPEG2, 11);
42184311
static MESON_GATE(g12a_uart2, HHI_GCLK_MPEG2, 15);
42194312
static MESON_GATE(g12a_vpu_intr, HHI_GCLK_MPEG2, 25);
4313+
static MESON_GATE(g12b_csi_phy1, HHI_GCLK_MPEG2, 28);
4314+
static MESON_GATE(g12b_csi_phy0, HHI_GCLK_MPEG2, 29);
42204315
static MESON_GATE(g12a_gic, HHI_GCLK_MPEG2, 30);
42214316

42224317
static MESON_GATE(g12a_vclk2_venci0, HHI_GCLK_OTHER, 1);
@@ -4407,10 +4502,12 @@ static struct clk_hw *g12a_hw_clks[] = {
44074502
[CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
44084503
[CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
44094504
[CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
4505+
[CLKID_CTS_ENCL_SEL] = &g12a_cts_encl_sel.hw,
44104506
[CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
44114507
[CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
44124508
[CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
44134509
[CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
4510+
[CLKID_CTS_ENCL] = &g12a_cts_encl.hw,
44144511
[CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
44154512
[CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
44164513
[CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
@@ -4632,10 +4729,12 @@ static struct clk_hw *g12b_hw_clks[] = {
46324729
[CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
46334730
[CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
46344731
[CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
4732+
[CLKID_CTS_ENCL_SEL] = &g12a_cts_encl_sel.hw,
46354733
[CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
46364734
[CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
46374735
[CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
46384736
[CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
4737+
[CLKID_CTS_ENCL] = &g12a_cts_encl.hw,
46394738
[CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
46404739
[CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
46414740
[CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
@@ -4729,6 +4828,12 @@ static struct clk_hw *g12b_hw_clks[] = {
47294828
[CLKID_MIPI_DSI_PXCLK_SEL] = &g12a_mipi_dsi_pxclk_sel.hw,
47304829
[CLKID_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw,
47314830
[CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw,
4831+
[CLKID_MIPI_ISP_SEL] = &g12b_mipi_isp_sel.hw,
4832+
[CLKID_MIPI_ISP_DIV] = &g12b_mipi_isp_div.hw,
4833+
[CLKID_MIPI_ISP] = &g12b_mipi_isp.hw,
4834+
[CLKID_MIPI_ISP_GATE] = &g12b_mipi_isp_gate.hw,
4835+
[CLKID_MIPI_ISP_CSI_PHY0] = &g12b_csi_phy0.hw,
4836+
[CLKID_MIPI_ISP_CSI_PHY1] = &g12b_csi_phy1.hw,
47324837
};
47334838

47344839
static struct clk_hw *sm1_hw_clks[] = {
@@ -4892,10 +4997,12 @@ static struct clk_hw *sm1_hw_clks[] = {
48924997
[CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
48934998
[CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
48944999
[CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
5000+
[CLKID_CTS_ENCL_SEL] = &g12a_cts_encl_sel.hw,
48955001
[CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
48965002
[CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
48975003
[CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
48985004
[CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
5005+
[CLKID_CTS_ENCL] = &g12a_cts_encl.hw,
48995006
[CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
49005007
[CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
49015008
[CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
@@ -5123,10 +5230,12 @@ static struct clk_regmap *const g12a_clk_regmaps[] = {
51235230
&g12a_vclk2_div12_en,
51245231
&g12a_cts_enci_sel,
51255232
&g12a_cts_encp_sel,
5233+
&g12a_cts_encl_sel,
51265234
&g12a_cts_vdac_sel,
51275235
&g12a_hdmi_tx_sel,
51285236
&g12a_cts_enci,
51295237
&g12a_cts_encp,
5238+
&g12a_cts_encl,
51305239
&g12a_cts_vdac,
51315240
&g12a_hdmi_tx,
51325241
&g12a_hdmi_sel,
@@ -5221,6 +5330,12 @@ static struct clk_regmap *const g12a_clk_regmaps[] = {
52215330
&g12a_mipi_dsi_pxclk_sel,
52225331
&g12a_mipi_dsi_pxclk_div,
52235332
&g12a_mipi_dsi_pxclk,
5333+
&g12b_mipi_isp_sel,
5334+
&g12b_mipi_isp_div,
5335+
&g12b_mipi_isp,
5336+
&g12b_mipi_isp_gate,
5337+
&g12b_csi_phy1,
5338+
&g12b_csi_phy0,
52245339
};
52255340

52265341
static const struct reg_sequence g12a_init_regs[] = {

‎drivers/clk/meson/g12a.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -70,6 +70,7 @@
7070
#define HHI_MALI_CLK_CNTL 0x1b0
7171
#define HHI_VPU_CLKC_CNTL 0x1b4
7272
#define HHI_VPU_CLK_CNTL 0x1bC
73+
#define HHI_ISP_CLK_CNTL 0x1C0
7374
#define HHI_NNA_CLK_CNTL 0x1C8
7475
#define HHI_HDMI_CLK_CNTL 0x1CC
7576
#define HHI_VDEC_CLK_CNTL 0x1E0

‎include/dt-bindings/clock/g12a-clkc.h‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -279,5 +279,13 @@
279279
#define CLKID_MIPI_DSI_PXCLK_DIV 268
280280
#define CLKID_MIPI_DSI_PXCLK_SEL 269
281281
#define CLKID_MIPI_DSI_PXCLK 270
282+
#define CLKID_CTS_ENCL 271
283+
#define CLKID_CTS_ENCL_SEL 272
284+
#define CLKID_MIPI_ISP_DIV 273
285+
#define CLKID_MIPI_ISP_SEL 274
286+
#define CLKID_MIPI_ISP 275
287+
#define CLKID_MIPI_ISP_GATE 276
288+
#define CLKID_MIPI_ISP_CSI_PHY0 277
289+
#define CLKID_MIPI_ISP_CSI_PHY1 278
282290

283291
#endif /* __G12A_CLKC_H */

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