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esmilConchuOD
esmil
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ConchuOD
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clk: starfive: Rename "jh7100" to "jh71x0" for the common code
Rename some variables from "jh7100" or "JH7100" to "jh71x0" or "JH71X0". Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
1 parent e19aa78 commit 147455e

4 files changed

Lines changed: 418 additions & 406 deletions

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‎drivers/clk/starfive/clk-starfive-jh7100-audio.c‎

Lines changed: 36 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -28,66 +28,66 @@
2828
#define JH7100_AUDCLK_I2SDAC_LRCLK_IOPAD (JH7100_AUDCLK_END + 6)
2929
#define JH7100_AUDCLK_VAD_INTMEM (JH7100_AUDCLK_END + 7)
3030

31-
static const struct jh7100_clk_data jh7100_audclk_data[] = {
32-
JH7100__GMD(JH7100_AUDCLK_ADC_MCLK, "adc_mclk", 0, 15, 2,
31+
static const struct jh71x0_clk_data jh7100_audclk_data[] = {
32+
JH71X0__GMD(JH7100_AUDCLK_ADC_MCLK, "adc_mclk", 0, 15, 2,
3333
JH7100_AUDCLK_AUDIO_SRC,
3434
JH7100_AUDCLK_AUDIO_12288),
35-
JH7100__GMD(JH7100_AUDCLK_I2S1_MCLK, "i2s1_mclk", 0, 15, 2,
35+
JH71X0__GMD(JH7100_AUDCLK_I2S1_MCLK, "i2s1_mclk", 0, 15, 2,
3636
JH7100_AUDCLK_AUDIO_SRC,
3737
JH7100_AUDCLK_AUDIO_12288),
38-
JH7100_GATE(JH7100_AUDCLK_I2SADC_APB, "i2sadc_apb", 0, JH7100_AUDCLK_APB0_BUS),
39-
JH7100_MDIV(JH7100_AUDCLK_I2SADC_BCLK, "i2sadc_bclk", 31, 2,
38+
JH71X0_GATE(JH7100_AUDCLK_I2SADC_APB, "i2sadc_apb", 0, JH7100_AUDCLK_APB0_BUS),
39+
JH71X0_MDIV(JH7100_AUDCLK_I2SADC_BCLK, "i2sadc_bclk", 31, 2,
4040
JH7100_AUDCLK_ADC_MCLK,
4141
JH7100_AUDCLK_I2SADC_BCLK_IOPAD),
42-
JH7100__INV(JH7100_AUDCLK_I2SADC_BCLK_N, "i2sadc_bclk_n", JH7100_AUDCLK_I2SADC_BCLK),
43-
JH7100_MDIV(JH7100_AUDCLK_I2SADC_LRCLK, "i2sadc_lrclk", 63, 3,
42+
JH71X0__INV(JH7100_AUDCLK_I2SADC_BCLK_N, "i2sadc_bclk_n", JH7100_AUDCLK_I2SADC_BCLK),
43+
JH71X0_MDIV(JH7100_AUDCLK_I2SADC_LRCLK, "i2sadc_lrclk", 63, 3,
4444
JH7100_AUDCLK_I2SADC_BCLK_N,
4545
JH7100_AUDCLK_I2SADC_LRCLK_IOPAD,
4646
JH7100_AUDCLK_I2SADC_BCLK),
47-
JH7100_GATE(JH7100_AUDCLK_PDM_APB, "pdm_apb", 0, JH7100_AUDCLK_APB0_BUS),
48-
JH7100__GMD(JH7100_AUDCLK_PDM_MCLK, "pdm_mclk", 0, 15, 2,
47+
JH71X0_GATE(JH7100_AUDCLK_PDM_APB, "pdm_apb", 0, JH7100_AUDCLK_APB0_BUS),
48+
JH71X0__GMD(JH7100_AUDCLK_PDM_MCLK, "pdm_mclk", 0, 15, 2,
4949
JH7100_AUDCLK_AUDIO_SRC,
5050
JH7100_AUDCLK_AUDIO_12288),
51-
JH7100_GATE(JH7100_AUDCLK_I2SVAD_APB, "i2svad_apb", 0, JH7100_AUDCLK_APB0_BUS),
52-
JH7100__GMD(JH7100_AUDCLK_SPDIF, "spdif", 0, 15, 2,
51+
JH71X0_GATE(JH7100_AUDCLK_I2SVAD_APB, "i2svad_apb", 0, JH7100_AUDCLK_APB0_BUS),
52+
JH71X0__GMD(JH7100_AUDCLK_SPDIF, "spdif", 0, 15, 2,
5353
JH7100_AUDCLK_AUDIO_SRC,
5454
JH7100_AUDCLK_AUDIO_12288),
55-
JH7100_GATE(JH7100_AUDCLK_SPDIF_APB, "spdif_apb", 0, JH7100_AUDCLK_APB0_BUS),
56-
JH7100_GATE(JH7100_AUDCLK_PWMDAC_APB, "pwmdac_apb", 0, JH7100_AUDCLK_APB0_BUS),
57-
JH7100__GMD(JH7100_AUDCLK_DAC_MCLK, "dac_mclk", 0, 15, 2,
55+
JH71X0_GATE(JH7100_AUDCLK_SPDIF_APB, "spdif_apb", 0, JH7100_AUDCLK_APB0_BUS),
56+
JH71X0_GATE(JH7100_AUDCLK_PWMDAC_APB, "pwmdac_apb", 0, JH7100_AUDCLK_APB0_BUS),
57+
JH71X0__GMD(JH7100_AUDCLK_DAC_MCLK, "dac_mclk", 0, 15, 2,
5858
JH7100_AUDCLK_AUDIO_SRC,
5959
JH7100_AUDCLK_AUDIO_12288),
60-
JH7100_GATE(JH7100_AUDCLK_I2SDAC_APB, "i2sdac_apb", 0, JH7100_AUDCLK_APB0_BUS),
61-
JH7100_MDIV(JH7100_AUDCLK_I2SDAC_BCLK, "i2sdac_bclk", 31, 2,
60+
JH71X0_GATE(JH7100_AUDCLK_I2SDAC_APB, "i2sdac_apb", 0, JH7100_AUDCLK_APB0_BUS),
61+
JH71X0_MDIV(JH7100_AUDCLK_I2SDAC_BCLK, "i2sdac_bclk", 31, 2,
6262
JH7100_AUDCLK_DAC_MCLK,
6363
JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),
64-
JH7100__INV(JH7100_AUDCLK_I2SDAC_BCLK_N, "i2sdac_bclk_n", JH7100_AUDCLK_I2SDAC_BCLK),
65-
JH7100_MDIV(JH7100_AUDCLK_I2SDAC_LRCLK, "i2sdac_lrclk", 31, 2,
64+
JH71X0__INV(JH7100_AUDCLK_I2SDAC_BCLK_N, "i2sdac_bclk_n", JH7100_AUDCLK_I2SDAC_BCLK),
65+
JH71X0_MDIV(JH7100_AUDCLK_I2SDAC_LRCLK, "i2sdac_lrclk", 31, 2,
6666
JH7100_AUDCLK_I2S1_MCLK,
6767
JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),
68-
JH7100_GATE(JH7100_AUDCLK_I2S1_APB, "i2s1_apb", 0, JH7100_AUDCLK_APB0_BUS),
69-
JH7100_MDIV(JH7100_AUDCLK_I2S1_BCLK, "i2s1_bclk", 31, 2,
68+
JH71X0_GATE(JH7100_AUDCLK_I2S1_APB, "i2s1_apb", 0, JH7100_AUDCLK_APB0_BUS),
69+
JH71X0_MDIV(JH7100_AUDCLK_I2S1_BCLK, "i2s1_bclk", 31, 2,
7070
JH7100_AUDCLK_I2S1_MCLK,
7171
JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),
72-
JH7100__INV(JH7100_AUDCLK_I2S1_BCLK_N, "i2s1_bclk_n", JH7100_AUDCLK_I2S1_BCLK),
73-
JH7100_MDIV(JH7100_AUDCLK_I2S1_LRCLK, "i2s1_lrclk", 63, 3,
72+
JH71X0__INV(JH7100_AUDCLK_I2S1_BCLK_N, "i2s1_bclk_n", JH7100_AUDCLK_I2S1_BCLK),
73+
JH71X0_MDIV(JH7100_AUDCLK_I2S1_LRCLK, "i2s1_lrclk", 63, 3,
7474
JH7100_AUDCLK_I2S1_BCLK_N,
7575
JH7100_AUDCLK_I2SDAC_LRCLK_IOPAD),
76-
JH7100_GATE(JH7100_AUDCLK_I2SDAC16K_APB, "i2s1dac16k_apb", 0, JH7100_AUDCLK_APB0_BUS),
77-
JH7100__DIV(JH7100_AUDCLK_APB0_BUS, "apb0_bus", 8, JH7100_AUDCLK_DOM7AHB_BUS),
78-
JH7100_GATE(JH7100_AUDCLK_DMA1P_AHB, "dma1p_ahb", 0, JH7100_AUDCLK_DOM7AHB_BUS),
79-
JH7100_GATE(JH7100_AUDCLK_USB_APB, "usb_apb", CLK_IGNORE_UNUSED, JH7100_AUDCLK_APB_EN),
80-
JH7100_GDIV(JH7100_AUDCLK_USB_LPM, "usb_lpm", CLK_IGNORE_UNUSED, 4, JH7100_AUDCLK_USB_APB),
81-
JH7100_GDIV(JH7100_AUDCLK_USB_STB, "usb_stb", CLK_IGNORE_UNUSED, 3, JH7100_AUDCLK_USB_APB),
82-
JH7100__DIV(JH7100_AUDCLK_APB_EN, "apb_en", 8, JH7100_AUDCLK_DOM7AHB_BUS),
83-
JH7100__MUX(JH7100_AUDCLK_VAD_MEM, "vad_mem", 2,
76+
JH71X0_GATE(JH7100_AUDCLK_I2SDAC16K_APB, "i2s1dac16k_apb", 0, JH7100_AUDCLK_APB0_BUS),
77+
JH71X0__DIV(JH7100_AUDCLK_APB0_BUS, "apb0_bus", 8, JH7100_AUDCLK_DOM7AHB_BUS),
78+
JH71X0_GATE(JH7100_AUDCLK_DMA1P_AHB, "dma1p_ahb", 0, JH7100_AUDCLK_DOM7AHB_BUS),
79+
JH71X0_GATE(JH7100_AUDCLK_USB_APB, "usb_apb", CLK_IGNORE_UNUSED, JH7100_AUDCLK_APB_EN),
80+
JH71X0_GDIV(JH7100_AUDCLK_USB_LPM, "usb_lpm", CLK_IGNORE_UNUSED, 4, JH7100_AUDCLK_USB_APB),
81+
JH71X0_GDIV(JH7100_AUDCLK_USB_STB, "usb_stb", CLK_IGNORE_UNUSED, 3, JH7100_AUDCLK_USB_APB),
82+
JH71X0__DIV(JH7100_AUDCLK_APB_EN, "apb_en", 8, JH7100_AUDCLK_DOM7AHB_BUS),
83+
JH71X0__MUX(JH7100_AUDCLK_VAD_MEM, "vad_mem", 2,
8484
JH7100_AUDCLK_VAD_INTMEM,
8585
JH7100_AUDCLK_AUDIO_12288),
8686
};
8787

8888
static struct clk_hw *jh7100_audclk_get(struct of_phandle_args *clkspec, void *data)
8989
{
90-
struct jh7100_clk_priv *priv = data;
90+
struct jh71x0_clk_priv *priv = data;
9191
unsigned int idx = clkspec->args[0];
9292

9393
if (idx < JH7100_AUDCLK_END)
@@ -98,7 +98,7 @@ static struct clk_hw *jh7100_audclk_get(struct of_phandle_args *clkspec, void *d
9898

9999
static int jh7100_audclk_probe(struct platform_device *pdev)
100100
{
101-
struct jh7100_clk_priv *priv;
101+
struct jh71x0_clk_priv *priv;
102102
unsigned int idx;
103103
int ret;
104104

@@ -117,12 +117,12 @@ static int jh7100_audclk_probe(struct platform_device *pdev)
117117
struct clk_parent_data parents[4] = {};
118118
struct clk_init_data init = {
119119
.name = jh7100_audclk_data[idx].name,
120-
.ops = starfive_jh7100_clk_ops(max),
120+
.ops = starfive_jh71x0_clk_ops(max),
121121
.parent_data = parents,
122-
.num_parents = ((max & JH7100_CLK_MUX_MASK) >> JH7100_CLK_MUX_SHIFT) + 1,
122+
.num_parents = ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1,
123123
.flags = jh7100_audclk_data[idx].flags,
124124
};
125-
struct jh7100_clk *clk = &priv->reg[idx];
125+
struct jh71x0_clk *clk = &priv->reg[idx];
126126
unsigned int i;
127127

128128
for (i = 0; i < init.num_parents; i++) {
@@ -140,7 +140,7 @@ static int jh7100_audclk_probe(struct platform_device *pdev)
140140

141141
clk->hw.init = &init;
142142
clk->idx = idx;
143-
clk->max_div = max & JH7100_CLK_DIV_MASK;
143+
clk->max_div = max & JH71X0_CLK_DIV_MASK;
144144

145145
ret = devm_clk_hw_register(priv->dev, &clk->hw);
146146
if (ret)

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