@@ -340,6 +340,123 @@ enum rk818_reg {
340340#define RK818_USB_ILMIN_2000MA 0x7
341341#define RK818_USB_CHG_SD_VSEL_MASK 0x70
342342
343+ /* RK801 */
344+ enum rk801_reg {
345+ RK801_ID_DCDC1 ,
346+ RK801_ID_DCDC2 ,
347+ RK801_ID_DCDC4 ,
348+ RK801_ID_DCDC3 ,
349+ RK801_ID_LDO1 ,
350+ RK801_ID_LDO2 ,
351+ RK801_ID_SWITCH ,
352+ RK801_ID_MAX ,
353+ };
354+
355+ #define RK801_SLP_REG_OFFSET 5
356+ #define RK801_NUM_REGULATORS 7
357+
358+ #define RK801_HW_SYNC_US 32
359+
360+ /* RK801 Register Definitions */
361+ #define RK801_ID_MSB 0x00
362+ #define RK801_ID_LSB 0x01
363+ #define RK801_OTP_VER_REG 0x02
364+ #define RK801_POWER_EN0_REG 0x03
365+ #define RK801_POWER_EN1_REG 0x04
366+ #define RK801_POWER_SLP_EN_REG 0x05
367+ #define RK801_POWER_FPWM_EN_REG 0x06
368+ #define RK801_SLP_LP_CONFIG_REG 0x07
369+ #define RK801_BUCK_CONFIG_REG 0x08
370+ #define RK801_BUCK1_ON_VSEL_REG 0x09
371+ #define RK801_BUCK2_ON_VSEL_REG 0x0a
372+ #define RK801_BUCK4_ON_VSEL_REG 0x0b
373+ #define RK801_LDO1_ON_VSEL_REG 0x0c
374+ #define RK801_LDO2_ON_VSEL_REG 0x0d
375+ #define RK801_BUCK1_SLP_VSEL_REG 0x0e
376+ #define RK801_BUCK2_SLP_VSEL_REG 0x0f
377+ #define RK801_BUCK4_SLP_VSEL_REG 0x10
378+ #define RK801_LDO1_SLP_VSEL_REG 0x11
379+ #define RK801_LDO2_SLP_VSEL_REG 0x12
380+ #define RK801_LDO_SW_IMAX_REG 0x13
381+ #define RK801_SYS_STS_REG 0x14
382+ #define RK801_SYS_CFG0_REG 0x15
383+ #define RK801_SYS_CFG1_REG 0x16
384+ #define RK801_SYS_CFG2_REG 0x17
385+ #define RK801_SYS_CFG3_REG 0x18
386+ #define RK801_SYS_CFG4_REG 0x19
387+ #define RK801_SLEEP_CFG_REG 0x1a
388+ #define RK801_ON_SOURCE_REG 0x1b
389+ #define RK801_OFF_SOURCE_REG 0x1c
390+ #define RK801_PWRON_KEY_REG 0x1d
391+ #define RK801_INT_STS0_REG 0x1e
392+ #define RK801_INT_MASK0_REG 0x1f
393+ #define RK801_INT_CONFIG_REG 0x20
394+ #define RK801_CON_BACK1_REG 0x21
395+ #define RK801_CON_BACK2_REG 0x22
396+ #define RK801_DATA_CON0_REG 0x23
397+ #define RK801_DATA_CON1_REG 0x24
398+ #define RK801_DATA_CON2_REG 0x25
399+ #define RK801_DATA_CON3_REG 0x26
400+ #define RK801_POWER_EXIT_SLP_SEQ0_REG 0x27
401+ #define RK801_POWER_EXIT_SLP_SEQ1_REG 0x28
402+ #define RK801_POWER_EXIT_SLP_SEQ2_REG 0x29
403+ #define RK801_POWER_EXIT_SLP_SEQ3_REG 0x2a
404+ #define RK801_POWER_ENTER_SLP_OR_SHTD_SEQ0_REG 0x2b
405+ #define RK801_POWER_ENTER_SLP_OR_SHTD_SEQ1_REG 0x2c
406+ #define RK801_POWER_ENTER_SLP_OR_SHTD_SEQ2_REG 0x2d
407+ #define RK801_POWER_ENTER_SLP_OR_SHTD_SEQ3_REG 0x2e
408+ #define RK801_BUCK_DEBUG1_REG 0x2f
409+ #define RK801_BUCK_DEBUG2_REG 0x30
410+ #define RK801_BUCK_DEBUG3_REG 0x31
411+ #define RK801_BUCK_DEBUG4_REG 0x32
412+ #define RK801_BUCK_DEBUG5_REG 0x33
413+ #define RK801_BUCK_DEBUG7_REG 0x34
414+ #define RK801_OTP_EN_CON_REG 0x35
415+ #define RK801_TEST_CON_REG 0x36
416+ #define RK801_EFUSE_CONTROL_REG 0x37
417+ #define RK801_SYS_CFG3_OTP_REG 0x38
418+
419+ /* RK801 IRQ Definitions */
420+ #define RK801_IRQ_PWRON_FALL 0
421+ #define RK801_IRQ_PWRON_RISE 1
422+ #define RK801_IRQ_PWRON 2
423+ #define RK801_IRQ_PWRON_LP 3
424+ #define RK801_IRQ_HOTDIE 4
425+ #define RK801_IRQ_VDC_RISE 5
426+ #define RK801_IRQ_VDC_FALL 6
427+ #define RK801_IRQ_PWRON_FALL_MSK BIT(0)
428+ #define RK801_IRQ_PWRON_RISE_MSK BIT(1)
429+ #define RK801_IRQ_PWRON_MSK BIT(2)
430+ #define RK801_IRQ_PWRON_LP_MSK BIT(3)
431+ #define RK801_IRQ_HOTDIE_MSK BIT(4)
432+ #define RK801_IRQ_VDC_RISE_MSK BIT(5)
433+ #define RK801_IRQ_VDC_FALL_MSK BIT(6)
434+ /* RK801_SLP_LP_CONFIG_REG */
435+ #define RK801_BUCK_SLP_LP_EN BIT(3)
436+ #define RK801_PLDO_SLP_LP_EN BIT(1)
437+ #define RK801_SLP_LP_MASK (RK801_PLDO_SLP_LP_EN | RK801_BUCK_SLP_LP_EN)
438+ /* RK801_SLEEP_CFG_REG */
439+ #define RK801_SLEEP_FUN_MSK 0x3
440+ #define RK801_NONE_FUN 0x0
441+ #define RK801_SLEEP_FUN 0x1
442+ #define RK801_SHUTDOWN_FUN 0x2
443+ #define RK801_RESET_FUN 0x3
444+ /* RK801_SYS_CFG2_REG */
445+ #define RK801_SLEEP_POL_MSK BIT(1)
446+ #define RK801_SLEEP_ACT_H BIT(1)
447+ #define RK801_SLEEP_ACT_L 0
448+ #define RK801_RST_MSK (0x3 << 4)
449+ #define RK801_RST_RESTART_PMU (0x0 << 4)
450+ #define RK801_RST_RESTART_REG (0x1 << 4)
451+ #define RK801_RST_RESTART_REG_RESETB (0x2 << 4)
452+ /* RK801_INT_CONFIG_REG */
453+ #define RK801_INT_POL_MSK BIT(1)
454+ #define RK801_INT_ACT_H BIT(1)
455+ #define RK801_INT_ACT_L 0
456+ #define RK801_FPWM_MODE 1
457+ #define RK801_AUTO_PWM_MODE 0
458+ #define RK801_PLDO_HRDEC_EN BIT(6)
459+
343460/* RK805 */
344461enum rk805_reg {
345462 RK805_ID_DCDC1 ,
@@ -1332,6 +1449,7 @@ enum {
13321449};
13331450
13341451enum {
1452+ RK801_ID = 0x8010 ,
13351453 RK805_ID = 0x8050 ,
13361454 RK806_ID = 0x8060 ,
13371455 RK808_ID = 0x0000 ,
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