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Marc Zyngier
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KVM: arm64: Add trap routing information for ICH_HCR_EL2
The usual song and dance. Anything that is a trap, any register it traps. Note that we don't handle the registers added by FEAT_NMI for now. Reviewed-by: Oliver Upton <oliver.upton@linux.dev> Link: https://lore.kernel.org/r/20240827152517.3909653-8-maz@kernel.org Signed-off-by: Marc Zyngier <maz@kernel.org>
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Lines changed: 66 additions & 5 deletions

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‎arch/arm64/kvm/emulate-nested.c‎

Lines changed: 66 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -85,12 +85,17 @@ enum cgt_group_id {
8585

8686
CGT_HCRX_TCR2En,
8787

88+
CGT_ICH_HCR_TC,
89+
CGT_ICH_HCR_TALL0,
90+
CGT_ICH_HCR_TALL1,
91+
CGT_ICH_HCR_TDIR,
92+
8893
/*
8994
* Anything after this point is a combination of coarse trap
9095
* controls, which must all be evaluated to decide what to do.
9196
*/
9297
__MULTIPLE_CONTROL_BITS__,
93-
CGT_HCR_IMO_FMO = __MULTIPLE_CONTROL_BITS__,
98+
CGT_HCR_IMO_FMO_ICH_HCR_TC = __MULTIPLE_CONTROL_BITS__,
9499
CGT_HCR_TID2_TID4,
95100
CGT_HCR_TTLB_TTLBIS,
96101
CGT_HCR_TTLB_TTLBOS,
@@ -105,6 +110,8 @@ enum cgt_group_id {
105110
CGT_MDCR_TDE_TDRA,
106111
CGT_MDCR_TDCC_TDE_TDA,
107112

113+
CGT_ICH_HCR_TC_TDIR,
114+
108115
/*
109116
* Anything after this point requires a callback evaluating a
110117
* complex trap condition. Ugly stuff.
@@ -378,6 +385,30 @@ static const struct trap_bits coarse_trap_bits[] = {
378385
.mask = HCRX_EL2_TCR2En,
379386
.behaviour = BEHAVE_FORWARD_ANY,
380387
},
388+
[CGT_ICH_HCR_TC] = {
389+
.index = ICH_HCR_EL2,
390+
.value = ICH_HCR_TC,
391+
.mask = ICH_HCR_TC,
392+
.behaviour = BEHAVE_FORWARD_ANY,
393+
},
394+
[CGT_ICH_HCR_TALL0] = {
395+
.index = ICH_HCR_EL2,
396+
.value = ICH_HCR_TALL0,
397+
.mask = ICH_HCR_TALL0,
398+
.behaviour = BEHAVE_FORWARD_ANY,
399+
},
400+
[CGT_ICH_HCR_TALL1] = {
401+
.index = ICH_HCR_EL2,
402+
.value = ICH_HCR_TALL1,
403+
.mask = ICH_HCR_TALL1,
404+
.behaviour = BEHAVE_FORWARD_ANY,
405+
},
406+
[CGT_ICH_HCR_TDIR] = {
407+
.index = ICH_HCR_EL2,
408+
.value = ICH_HCR_TDIR,
409+
.mask = ICH_HCR_TDIR,
410+
.behaviour = BEHAVE_FORWARD_ANY,
411+
},
381412
};
382413

383414
#define MCB(id, ...) \
@@ -387,7 +418,6 @@ static const struct trap_bits coarse_trap_bits[] = {
387418
}
388419

389420
static const enum cgt_group_id *coarse_control_combo[] = {
390-
MCB(CGT_HCR_IMO_FMO, CGT_HCR_IMO, CGT_HCR_FMO),
391421
MCB(CGT_HCR_TID2_TID4, CGT_HCR_TID2, CGT_HCR_TID4),
392422
MCB(CGT_HCR_TTLB_TTLBIS, CGT_HCR_TTLB, CGT_HCR_TTLBIS),
393423
MCB(CGT_HCR_TTLB_TTLBOS, CGT_HCR_TTLB, CGT_HCR_TTLBOS),
@@ -402,6 +432,9 @@ static const enum cgt_group_id *coarse_control_combo[] = {
402432
MCB(CGT_MDCR_TDE_TDOSA, CGT_MDCR_TDE, CGT_MDCR_TDOSA),
403433
MCB(CGT_MDCR_TDE_TDRA, CGT_MDCR_TDE, CGT_MDCR_TDRA),
404434
MCB(CGT_MDCR_TDCC_TDE_TDA, CGT_MDCR_TDCC, CGT_MDCR_TDE, CGT_MDCR_TDA),
435+
436+
MCB(CGT_HCR_IMO_FMO_ICH_HCR_TC, CGT_HCR_IMO, CGT_HCR_FMO, CGT_ICH_HCR_TC),
437+
MCB(CGT_ICH_HCR_TC_TDIR, CGT_ICH_HCR_TC, CGT_ICH_HCR_TDIR),
405438
};
406439

407440
typedef enum trap_behaviour (*complex_condition_check)(struct kvm_vcpu *);
@@ -536,9 +569,9 @@ static const struct encoding_to_trap_config encoding_to_cgt[] __initconst = {
536569
SR_TRAP(SYS_CSSELR_EL1, CGT_HCR_TID2_TID4),
537570
SR_RANGE_TRAP(SYS_ID_PFR0_EL1,
538571
sys_reg(3, 0, 0, 7, 7), CGT_HCR_TID3),
539-
SR_TRAP(SYS_ICC_SGI0R_EL1, CGT_HCR_IMO_FMO),
540-
SR_TRAP(SYS_ICC_ASGI1R_EL1, CGT_HCR_IMO_FMO),
541-
SR_TRAP(SYS_ICC_SGI1R_EL1, CGT_HCR_IMO_FMO),
572+
SR_TRAP(SYS_ICC_SGI0R_EL1, CGT_HCR_IMO_FMO_ICH_HCR_TC),
573+
SR_TRAP(SYS_ICC_ASGI1R_EL1, CGT_HCR_IMO_FMO_ICH_HCR_TC),
574+
SR_TRAP(SYS_ICC_SGI1R_EL1, CGT_HCR_IMO_FMO_ICH_HCR_TC),
542575
SR_RANGE_TRAP(sys_reg(3, 0, 11, 0, 0),
543576
sys_reg(3, 0, 11, 15, 7), CGT_HCR_TIDCP),
544577
SR_RANGE_TRAP(sys_reg(3, 1, 11, 0, 0),
@@ -1108,6 +1141,34 @@ static const struct encoding_to_trap_config encoding_to_cgt[] __initconst = {
11081141
SR_TRAP(SYS_CNTP_CTL_EL0, CGT_CNTHCTL_EL1PTEN),
11091142
SR_TRAP(SYS_CNTPCT_EL0, CGT_CNTHCTL_EL1PCTEN),
11101143
SR_TRAP(SYS_CNTPCTSS_EL0, CGT_CNTHCTL_EL1PCTEN),
1144+
/*
1145+
* IMPDEF choice:
1146+
* We treat ICC_SRE_EL2.{SRE,Enable) and ICV_SRE_EL1.SRE as
1147+
* RAO/WI. We therefore never consider ICC_SRE_EL2.Enable for
1148+
* ICC_SRE_EL1 access, and always handle it locally.
1149+
*/
1150+
SR_TRAP(SYS_ICC_AP0R0_EL1, CGT_ICH_HCR_TALL0),
1151+
SR_TRAP(SYS_ICC_AP0R1_EL1, CGT_ICH_HCR_TALL0),
1152+
SR_TRAP(SYS_ICC_AP0R2_EL1, CGT_ICH_HCR_TALL0),
1153+
SR_TRAP(SYS_ICC_AP0R3_EL1, CGT_ICH_HCR_TALL0),
1154+
SR_TRAP(SYS_ICC_AP1R0_EL1, CGT_ICH_HCR_TALL1),
1155+
SR_TRAP(SYS_ICC_AP1R1_EL1, CGT_ICH_HCR_TALL1),
1156+
SR_TRAP(SYS_ICC_AP1R2_EL1, CGT_ICH_HCR_TALL1),
1157+
SR_TRAP(SYS_ICC_AP1R3_EL1, CGT_ICH_HCR_TALL1),
1158+
SR_TRAP(SYS_ICC_BPR0_EL1, CGT_ICH_HCR_TALL0),
1159+
SR_TRAP(SYS_ICC_BPR1_EL1, CGT_ICH_HCR_TALL1),
1160+
SR_TRAP(SYS_ICC_CTLR_EL1, CGT_ICH_HCR_TC),
1161+
SR_TRAP(SYS_ICC_DIR_EL1, CGT_ICH_HCR_TC_TDIR),
1162+
SR_TRAP(SYS_ICC_EOIR0_EL1, CGT_ICH_HCR_TALL0),
1163+
SR_TRAP(SYS_ICC_EOIR1_EL1, CGT_ICH_HCR_TALL1),
1164+
SR_TRAP(SYS_ICC_HPPIR0_EL1, CGT_ICH_HCR_TALL0),
1165+
SR_TRAP(SYS_ICC_HPPIR1_EL1, CGT_ICH_HCR_TALL1),
1166+
SR_TRAP(SYS_ICC_IAR0_EL1, CGT_ICH_HCR_TALL0),
1167+
SR_TRAP(SYS_ICC_IAR1_EL1, CGT_ICH_HCR_TALL1),
1168+
SR_TRAP(SYS_ICC_IGRPEN0_EL1, CGT_ICH_HCR_TALL0),
1169+
SR_TRAP(SYS_ICC_IGRPEN1_EL1, CGT_ICH_HCR_TALL1),
1170+
SR_TRAP(SYS_ICC_PMR_EL1, CGT_ICH_HCR_TC),
1171+
SR_TRAP(SYS_ICC_RPR_EL1, CGT_ICH_HCR_TC),
11111172
};
11121173

11131174
static DEFINE_XARRAY(sr_forward_xa);

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