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kwachowsStanislaw Gruszka
kwachows
authored and
Stanislaw Gruszka
committed
accel/ivpu: Refactor memory ranges logic
Add new dma range and change naming convention for virtual address memory ranges managed by KMD. New available ranges are named as follows: * global range - global context accessible by FW * aliased range - user context accessible by FW * dma range - user context accessible by DMA * shave range - user context accessible by shaves * global shave range - global context accessible by shave nn Signed-off-by: Karol Wachowski <karol.wachowski@linux.intel.com> Reviewed-by: Stanislaw Gruszka <stanislaw.gruszka@linux.intel.com> Signed-off-by: Stanislaw Gruszka <stanislaw.gruszka@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230731161258.2987564-6-stanislaw.gruszka@linux.intel.com
1 parent aa5f04d commit 162f17b

7 files changed

Lines changed: 32 additions & 31 deletions

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‎drivers/accel/ivpu/ivpu_drv.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -122,7 +122,7 @@ static int ivpu_get_capabilities(struct ivpu_device *vdev, struct drm_ivpu_param
122122
args->value = 0;
123123
break;
124124
case DRM_IVPU_CAP_DMA_MEMORY_RANGE:
125-
args->value = 0;
125+
args->value = 1;
126126
break;
127127
default:
128128
return -EINVAL;
@@ -160,7 +160,7 @@ static int ivpu_get_param_ioctl(struct drm_device *dev, void *data, struct drm_f
160160
args->value = ivpu_get_context_count(vdev);
161161
break;
162162
case DRM_IVPU_PARAM_CONTEXT_BASE_ADDRESS:
163-
args->value = vdev->hw->ranges.user_low.start;
163+
args->value = vdev->hw->ranges.user.start;
164164
break;
165165
case DRM_IVPU_PARAM_CONTEXT_PRIORITY:
166166
args->value = file_priv->priority;

‎drivers/accel/ivpu/ivpu_fw.c‎

Lines changed: 8 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -204,7 +204,7 @@ static int ivpu_fw_update_global_range(struct ivpu_device *vdev)
204204
return -EINVAL;
205205
}
206206

207-
ivpu_hw_init_range(&vdev->hw->ranges.global_low, start, size);
207+
ivpu_hw_init_range(&vdev->hw->ranges.global, start, size);
208208
return 0;
209209
}
210210

@@ -245,7 +245,7 @@ static int ivpu_fw_mem_init(struct ivpu_device *vdev)
245245
}
246246

247247
if (fw->shave_nn_size) {
248-
fw->mem_shave_nn = ivpu_bo_alloc_internal(vdev, vdev->hw->ranges.global_high.start,
248+
fw->mem_shave_nn = ivpu_bo_alloc_internal(vdev, vdev->hw->ranges.shave.start,
249249
fw->shave_nn_size, DRM_IVPU_BO_UNCACHED);
250250
if (!fw->mem_shave_nn) {
251251
ivpu_err(vdev, "Failed to allocate shavenn buffer\n");
@@ -443,28 +443,26 @@ void ivpu_fw_boot_params_setup(struct ivpu_device *vdev, struct vpu_boot_params
443443
* Uncached region of VPU address space, covers IPC buffers, job queues
444444
* and log buffers, programmable to L2$ Uncached by VPU MTRR
445445
*/
446-
boot_params->shared_region_base = vdev->hw->ranges.global_low.start;
447-
boot_params->shared_region_size = vdev->hw->ranges.global_low.end -
448-
vdev->hw->ranges.global_low.start;
446+
boot_params->shared_region_base = vdev->hw->ranges.global.start;
447+
boot_params->shared_region_size = vdev->hw->ranges.global.end -
448+
vdev->hw->ranges.global.start;
449449

450450
boot_params->ipc_header_area_start = ipc_mem_rx->vpu_addr;
451451
boot_params->ipc_header_area_size = ipc_mem_rx->base.size / 2;
452452

453453
boot_params->ipc_payload_area_start = ipc_mem_rx->vpu_addr + ipc_mem_rx->base.size / 2;
454454
boot_params->ipc_payload_area_size = ipc_mem_rx->base.size / 2;
455455

456-
boot_params->global_aliased_pio_base =
457-
vdev->hw->ranges.global_aliased_pio.start;
458-
boot_params->global_aliased_pio_size =
459-
ivpu_hw_range_size(&vdev->hw->ranges.global_aliased_pio);
456+
boot_params->global_aliased_pio_base = vdev->hw->ranges.user.start;
457+
boot_params->global_aliased_pio_size = ivpu_hw_range_size(&vdev->hw->ranges.user);
460458

461459
/* Allow configuration for L2C_PAGE_TABLE with boot param value */
462460
boot_params->autoconfig = 1;
463461

464462
/* Enable L2 cache for first 2GB of high memory */
465463
boot_params->cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].use = 1;
466464
boot_params->cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].cfg =
467-
ADDR_TO_L2_CACHE_CFG(vdev->hw->ranges.global_high.start);
465+
ADDR_TO_L2_CACHE_CFG(vdev->hw->ranges.shave.start);
468466

469467
if (vdev->fw->mem_shave_nn)
470468
boot_params->shave_nn_fw_base = vdev->fw->mem_shave_nn->vpu_addr;

‎drivers/accel/ivpu/ivpu_gem.c‎

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -279,10 +279,12 @@ ivpu_bo_alloc_vpu_addr(struct ivpu_bo *bo, struct ivpu_mmu_context *ctx,
279279
int ret;
280280

281281
if (!range) {
282-
if (bo->flags & DRM_IVPU_BO_HIGH_MEM)
283-
range = &vdev->hw->ranges.user_high;
282+
if (bo->flags & DRM_IVPU_BO_SHAVE_MEM)
283+
range = &vdev->hw->ranges.shave;
284+
else if (bo->flags & DRM_IVPU_BO_DMA_MEM)
285+
range = &vdev->hw->ranges.dma;
284286
else
285-
range = &vdev->hw->ranges.user_low;
287+
range = &vdev->hw->ranges.user;
286288
}
287289

288290
mutex_lock(&ctx->lock);
@@ -570,7 +572,7 @@ ivpu_bo_alloc_internal(struct ivpu_device *vdev, u64 vpu_addr, u64 size, u32 fla
570572
fixed_range.end = vpu_addr + size;
571573
range = &fixed_range;
572574
} else {
573-
range = &vdev->hw->ranges.global_low;
575+
range = &vdev->hw->ranges.global;
574576
}
575577

576578
bo = ivpu_bo_alloc(vdev, &vdev->gctx, size, flags, &internal_ops, range, 0);

‎drivers/accel/ivpu/ivpu_hw.h‎

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -38,11 +38,10 @@ struct ivpu_addr_range {
3838
struct ivpu_hw_info {
3939
const struct ivpu_hw_ops *ops;
4040
struct {
41-
struct ivpu_addr_range global_low;
42-
struct ivpu_addr_range global_high;
43-
struct ivpu_addr_range user_low;
44-
struct ivpu_addr_range user_high;
45-
struct ivpu_addr_range global_aliased_pio;
41+
struct ivpu_addr_range global;
42+
struct ivpu_addr_range user;
43+
struct ivpu_addr_range shave;
44+
struct ivpu_addr_range dma;
4645
} ranges;
4746
struct {
4847
u8 min_ratio;

‎drivers/accel/ivpu/ivpu_hw_37xx.c‎

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -620,11 +620,10 @@ static int ivpu_hw_37xx_info_init(struct ivpu_device *vdev)
620620

621621
ivpu_pll_init_frequency_ratios(vdev);
622622

623-
ivpu_hw_init_range(&hw->ranges.global_low, 0x80000000, SZ_512M);
624-
ivpu_hw_init_range(&hw->ranges.global_high, 0x180000000, SZ_2M);
625-
ivpu_hw_init_range(&hw->ranges.user_low, 0xc0000000, 255 * SZ_1M);
626-
ivpu_hw_init_range(&hw->ranges.user_high, 0x180000000, SZ_2G);
627-
hw->ranges.global_aliased_pio = hw->ranges.user_low;
623+
ivpu_hw_init_range(&hw->ranges.global, 0x80000000, SZ_512M);
624+
ivpu_hw_init_range(&hw->ranges.user, 0xc0000000, 255 * SZ_1M);
625+
ivpu_hw_init_range(&hw->ranges.shave, 0x180000000, SZ_2G);
626+
ivpu_hw_init_range(&hw->ranges.dma, 0x200000000, SZ_8G);
628627

629628
return 0;
630629
}

‎drivers/accel/ivpu/ivpu_mmu_context.c‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -431,11 +431,11 @@ ivpu_mmu_context_init(struct ivpu_device *vdev, struct ivpu_mmu_context *ctx, u3
431431
return ret;
432432

433433
if (!context_id) {
434-
start = vdev->hw->ranges.global_low.start;
435-
end = vdev->hw->ranges.global_high.end;
434+
start = vdev->hw->ranges.global.start;
435+
end = vdev->hw->ranges.shave.end;
436436
} else {
437-
start = vdev->hw->ranges.user_low.start;
438-
end = vdev->hw->ranges.user_high.end;
437+
start = vdev->hw->ranges.user.start;
438+
end = vdev->hw->ranges.dma.end;
439439
}
440440

441441
drm_mm_init(&ctx->mm, start, end - start);

‎include/uapi/drm/ivpu_accel.h‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -133,8 +133,10 @@ struct drm_ivpu_param {
133133
__u64 value;
134134
};
135135

136-
#define DRM_IVPU_BO_HIGH_MEM 0x00000001
136+
#define DRM_IVPU_BO_SHAVE_MEM 0x00000001
137+
#define DRM_IVPU_BO_HIGH_MEM DRM_IVPU_BO_SHAVE_MEM
137138
#define DRM_IVPU_BO_MAPPABLE 0x00000002
139+
#define DRM_IVPU_BO_DMA_MEM 0x00000004
138140

139141
#define DRM_IVPU_BO_CACHED 0x00000000
140142
#define DRM_IVPU_BO_UNCACHED 0x00010000
@@ -144,6 +146,7 @@ struct drm_ivpu_param {
144146
#define DRM_IVPU_BO_FLAGS \
145147
(DRM_IVPU_BO_HIGH_MEM | \
146148
DRM_IVPU_BO_MAPPABLE | \
149+
DRM_IVPU_BO_DMA_MEM | \
147150
DRM_IVPU_BO_CACHE_MASK)
148151

149152
/**

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