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219 | 219 | #define X86_FEATURE_IBRS ( 7*32+25) /* Indirect Branch Restricted Speculation */ |
220 | 220 | #define X86_FEATURE_IBPB ( 7*32+26) /* Indirect Branch Prediction Barrier */ |
221 | 221 | #define X86_FEATURE_STIBP ( 7*32+27) /* Single Thread Indirect Branch Predictors */ |
222 | | -#define X86_FEATURE_ZEN ( 7*32+28) /* "" CPU is AMD family 0x17 or above (Zen) */ |
| 222 | +#define X86_FEATURE_ZEN (7*32+28) /* "" CPU based on Zen microarchitecture */ |
223 | 223 | #define X86_FEATURE_L1TF_PTEINV ( 7*32+29) /* "" L1TF workaround PTE inversion */ |
224 | 224 | #define X86_FEATURE_IBRS_ENHANCED ( 7*32+30) /* Enhanced IBRS */ |
225 | 225 | #define X86_FEATURE_MSR_IA32_FEAT_CTL ( 7*32+31) /* "" MSR IA32_FEAT_CTL configured */ |
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303 | 303 | #define X86_FEATURE_RETHUNK (11*32+14) /* "" Use REturn THUNK */ |
304 | 304 | #define X86_FEATURE_UNRET (11*32+15) /* "" AMD BTB untrain return */ |
305 | 305 | #define X86_FEATURE_USE_IBPB_FW (11*32+16) /* "" Use IBPB during runtime firmware calls */ |
306 | | -#define X86_FEATURE_RSB_VMEXIT_LITE (11*32+17) /* "" Fill RSB on VM-Exit when EIBRS is enabled */ |
| 306 | +#define X86_FEATURE_RSB_VMEXIT_LITE (11*32+17) /* "" Fill RSB on VM exit when EIBRS is enabled */ |
307 | 307 |
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308 | 308 | /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */ |
309 | 309 | #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */ |
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354 | 354 | #define X86_FEATURE_AVIC (15*32+13) /* Virtual Interrupt Controller */ |
355 | 355 | #define X86_FEATURE_V_VMSAVE_VMLOAD (15*32+15) /* Virtual VMSAVE VMLOAD */ |
356 | 356 | #define X86_FEATURE_VGIF (15*32+16) /* Virtual GIF */ |
| 357 | +#define X86_FEATURE_X2AVIC (15*32+18) /* Virtual x2apic */ |
357 | 358 | #define X86_FEATURE_V_SPEC_CTRL (15*32+20) /* Virtual SPEC_CTRL */ |
358 | 359 | #define X86_FEATURE_SVME_ADDR_CHK (15*32+28) /* "" SVME addr check */ |
359 | 360 |
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457 | 458 | #define X86_BUG_SRBDS X86_BUG(24) /* CPU may leak RNG bits if not mitigated */ |
458 | 459 | #define X86_BUG_MMIO_STALE_DATA X86_BUG(25) /* CPU is affected by Processor MMIO Stale Data vulnerabilities */ |
459 | 460 | #define X86_BUG_RETBLEED X86_BUG(26) /* CPU is affected by RETBleed */ |
| 461 | +#define X86_BUG_EIBRS_PBRSB X86_BUG(27) /* EIBRS is vulnerable to Post Barrier RSB Predictions */ |
460 | 462 |
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461 | 463 | #endif /* _ASM_X86_CPUFEATURES_H */ |
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