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Yann-lmsUlf Hansson
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mmc: mmci: stm32: set feedback clock when using delay block
The feedback clock is used only for SDR104 & HS200 modes, and when delay block is used (frequency is higher than 50 MHz). The tuning procedure is then only required for those modes. Skip the procedure for other modes. The setting of this feedback clock is done just after enabling delay block, and before configuring it. Signed-off-by: Yann Gautier <yann.gautier@foss.st.com> Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com> Link: https://lore.kernel.org/r/20230613150148.429828-1-yann.gautier@foss.st.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
1 parent 2cc83bf commit 16f2e6c

1 file changed

Lines changed: 18 additions & 11 deletions

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drivers/mmc/host/mmci_stm32_sdmmc.c

Lines changed: 18 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -293,18 +293,8 @@ static void mmci_sdmmc_set_clkreg(struct mmci_host *host, unsigned int desired)
293293
clk |= host->clk_reg_add;
294294
clk |= ddr;
295295

296-
/*
297-
* SDMMC_FBCK is selected when an external Delay Block is needed
298-
* with SDR104 or HS200.
299-
*/
300-
if (host->mmc->ios.timing >= MMC_TIMING_UHS_SDR50) {
296+
if (host->mmc->ios.timing >= MMC_TIMING_UHS_SDR50)
301297
clk |= MCI_STM32_CLK_BUSSPEED;
302-
if (host->mmc->ios.timing == MMC_TIMING_UHS_SDR104 ||
303-
host->mmc->ios.timing == MMC_TIMING_MMC_HS200) {
304-
clk &= ~MCI_STM32_CLK_SEL_MSK;
305-
clk |= MCI_STM32_CLK_SELFBCK;
306-
}
307-
}
308298

309299
mmci_write_clkreg(host, clk);
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}
@@ -511,10 +501,27 @@ static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode)
511501
{
512502
struct mmci_host *host = mmc_priv(mmc);
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struct sdmmc_dlyb *dlyb = host->variant_priv;
504+
u32 clk;
505+
506+
if ((host->mmc->ios.timing != MMC_TIMING_UHS_SDR104 &&
507+
host->mmc->ios.timing != MMC_TIMING_MMC_HS200) ||
508+
host->mmc->actual_clock <= 50000000)
509+
return 0;
514510

515511
if (!dlyb || !dlyb->base)
516512
return -EINVAL;
517513

514+
writel_relaxed(DLYB_CR_DEN, dlyb->base + DLYB_CR);
515+
516+
/*
517+
* SDMMC_FBCK is selected when an external Delay Block is needed
518+
* with SDR104 or HS200.
519+
*/
520+
clk = host->clk_reg;
521+
clk &= ~MCI_STM32_CLK_SEL_MSK;
522+
clk |= MCI_STM32_CLK_SELFBCK;
523+
mmci_write_clkreg(host, clk);
524+
518525
if (sdmmc_dlyb_lng_tuning(host))
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return -EINVAL;
520527

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