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Merge tag 'renesas-dts-for-v6.4-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
Renesas DTS updates for v6.4 (take two) - Add PWM support for the R-Car H1 and H2 SoCs, - Add slide switch and I2C support for the Marzen development board, - Add SCI (serial) and Camera support for the RZ/G2L SoC and the RZ/G2L SMARC EVK development board, - Add IOMMU support for the R-Car V4H SoC, - Miscellaneous fixes and improvements. * tag 'renesas-dts-for-v6.4-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: arm64: dts: renesas: r8a779a0: Revise renesas,ipmmu-main arm64: dts: renesas: falcon-csi-dsi: Set bus-type for MAX96712 arm64: dts: renesas: r8a779g0: Add iommus to MMC node arm64: dts: renesas: r8a779g0: Add iommus to DMAC nodes arm64: dts: renesas: r8a779g0: Add IPMMU nodes arm64: dts: renesas: r8a779f0: Revise renesas,ipmmu-main arm64: dts: renesas: rzg2l-smarc: Enable CRU, CSI support arm64: dts: renesas: r9a07g044: Add CSI and CRU nodes arm64: dts: renesas: r9a07g044: Enable SCI0 using DT overlay ARM: dts: r8a7790: Add PWM device nodes ARM: dts: r8a7790: Add TPU device node ARM: dts: marzen: Enable I2C support ARM: dts: marzen: Add slide switches ARM: dts: r8a7779: Add PWM support dt-bindings: clock: r8a7779: Add PWM module clock arm64: dts: renesas: rzg2l: Add clock-names and reset-names to DMAC nodes Link: https://lore.kernel.org/r/cover.1681113117.git.geert+renesas@glider.be Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2 parents 2925732 + 2f04079 commit 17e26de

15 files changed

Lines changed: 608 additions & 28 deletions

‎arch/arm/boot/dts/r8a7779-marzen.dts‎

Lines changed: 69 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,7 @@
99
/dts-v1/;
1010
#include "r8a7779.dtsi"
1111
#include <dt-bindings/gpio/gpio.h>
12+
#include <dt-bindings/input/input.h>
1213
#include <dt-bindings/interrupt-controller/irq.h>
1314

1415
/ {
@@ -66,6 +67,51 @@
6667
vdd33a-supply = <&fixedregulator3v3>;
6768
};
6869

70+
keyboard-irq {
71+
compatible = "gpio-keys";
72+
73+
pinctrl-0 = <&keyboard_irq_pins>;
74+
pinctrl-names = "default";
75+
76+
interrupt-parent = <&gpio0>;
77+
78+
key-1 {
79+
interrupts = <17 IRQ_TYPE_EDGE_FALLING>;
80+
linux,code = <KEY_1>;
81+
label = "SW1-1";
82+
wakeup-source;
83+
debounce-interval = <20>;
84+
};
85+
key-2 {
86+
interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
87+
linux,code = <KEY_2>;
88+
label = "SW1-2";
89+
wakeup-source;
90+
debounce-interval = <20>;
91+
};
92+
};
93+
94+
keyboard-gpio {
95+
compatible = "gpio-keys-polled";
96+
poll-interval = <50>;
97+
98+
pinctrl-0 = <&keyboard_gpio_pins>;
99+
pinctrl-names = "default";
100+
101+
key-3 {
102+
gpios = <&gpio0 19 GPIO_ACTIVE_LOW>;
103+
linux,code = <KEY_3>;
104+
label = "SW1-3";
105+
debounce-interval = <20>;
106+
};
107+
key-4 {
108+
gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
109+
linux,code = <KEY_4>;
110+
label = "SW1-4";
111+
debounce-interval = <20>;
112+
};
113+
};
114+
69115
leds {
70116
compatible = "gpio-leds";
71117
led2 {
@@ -161,6 +207,20 @@
161207
};
162208
};
163209

210+
&gpio0 {
211+
keyboard-irq-hog {
212+
gpio-hog;
213+
gpios = <17 GPIO_ACTIVE_LOW>, <18 GPIO_ACTIVE_LOW>;
214+
input;
215+
};
216+
};
217+
218+
&i2c0 {
219+
status = "okay";
220+
221+
clock-frequency = <100000>;
222+
};
223+
164224
&irqpin0 {
165225
status = "okay";
166226
};
@@ -223,6 +283,15 @@
223283
groups = "hspi0";
224284
function = "hspi0";
225285
};
286+
287+
keyboard_irq_pins: keyboard-irq {
288+
pins = "GP_0_17", "GP_0_18";
289+
bias-pull-up;
290+
};
291+
keyboard_gpio_pins: keyboard-gpio {
292+
pins = "GP_0_19", "GP_0_20";
293+
bias-pull-up;
294+
};
226295
};
227296

228297
&sata {

‎arch/arm/boot/dts/r8a7779.dtsi‎

Lines changed: 78 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -324,6 +324,69 @@
324324
status = "disabled";
325325
};
326326

327+
pwm0: pwm@ffe50000 {
328+
compatible = "renesas,pwm-r8a7779", "renesas,pwm-rcar";
329+
reg = <0xffe50000 0x8>;
330+
clocks = <&mstp0_clks R8A7779_CLK_PWM>;
331+
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
332+
#pwm-cells = <2>;
333+
status = "disabled";
334+
};
335+
336+
pwm1: pwm@ffe51000 {
337+
compatible = "renesas,pwm-r8a7779", "renesas,pwm-rcar";
338+
reg = <0xffe51000 0x8>;
339+
clocks = <&mstp0_clks R8A7779_CLK_PWM>;
340+
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
341+
#pwm-cells = <2>;
342+
status = "disabled";
343+
};
344+
345+
pwm2: pwm@ffe52000 {
346+
compatible = "renesas,pwm-r8a7779", "renesas,pwm-rcar";
347+
reg = <0xffe52000 0x8>;
348+
clocks = <&mstp0_clks R8A7779_CLK_PWM>;
349+
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
350+
#pwm-cells = <2>;
351+
status = "disabled";
352+
};
353+
354+
pwm3: pwm@ffe53000 {
355+
compatible = "renesas,pwm-r8a7779", "renesas,pwm-rcar";
356+
reg = <0xffe53000 0x8>;
357+
clocks = <&mstp0_clks R8A7779_CLK_PWM>;
358+
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
359+
#pwm-cells = <2>;
360+
status = "disabled";
361+
};
362+
363+
pwm4: pwm@ffe54000 {
364+
compatible = "renesas,pwm-r8a7779", "renesas,pwm-rcar";
365+
reg = <0xffe54000 0x8>;
366+
clocks = <&mstp0_clks R8A7779_CLK_PWM>;
367+
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
368+
#pwm-cells = <2>;
369+
status = "disabled";
370+
};
371+
372+
pwm5: pwm@ffe55000 {
373+
compatible = "renesas,pwm-r8a7779", "renesas,pwm-rcar";
374+
reg = <0xffe55000 0x8>;
375+
clocks = <&mstp0_clks R8A7779_CLK_PWM>;
376+
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
377+
#pwm-cells = <2>;
378+
status = "disabled";
379+
};
380+
381+
pwm6: pwm@ffe56000 {
382+
compatible = "renesas,pwm-r8a7779", "renesas,pwm-rcar";
383+
reg = <0xffe56000 0x8>;
384+
clocks = <&mstp0_clks R8A7779_CLK_PWM>;
385+
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
386+
#pwm-cells = <2>;
387+
status = "disabled";
388+
};
389+
327390
pfc: pinctrl@fffc0000 {
328391
compatible = "renesas,pfc-r8a7779";
329392
reg = <0xfffc0000 0x23c>;
@@ -554,7 +617,8 @@
554617
compatible = "renesas,r8a7779-mstp-clocks",
555618
"renesas,cpg-mstp-clocks";
556619
reg = <0xffc80030 4>;
557-
clocks = <&cpg_clocks R8A7779_CLK_S>,
620+
clocks = <&cpg_clocks R8A7779_CLK_P>,
621+
<&cpg_clocks R8A7779_CLK_S>,
558622
<&cpg_clocks R8A7779_CLK_P>,
559623
<&cpg_clocks R8A7779_CLK_P>,
560624
<&cpg_clocks R8A7779_CLK_P>,
@@ -572,20 +636,21 @@
572636
<&cpg_clocks R8A7779_CLK_P>;
573637
#clock-cells = <1>;
574638
clock-indices = <
575-
R8A7779_CLK_HSPI R8A7779_CLK_TMU2
576-
R8A7779_CLK_TMU1 R8A7779_CLK_TMU0
577-
R8A7779_CLK_HSCIF1 R8A7779_CLK_HSCIF0
578-
R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4
579-
R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2
580-
R8A7779_CLK_SCIF1 R8A7779_CLK_SCIF0
581-
R8A7779_CLK_I2C3 R8A7779_CLK_I2C2
582-
R8A7779_CLK_I2C1 R8A7779_CLK_I2C0
639+
R8A7779_CLK_PWM R8A7779_CLK_HSPI
640+
R8A7779_CLK_TMU2 R8A7779_CLK_TMU1
641+
R8A7779_CLK_TMU0 R8A7779_CLK_HSCIF1
642+
R8A7779_CLK_HSCIF0 R8A7779_CLK_SCIF5
643+
R8A7779_CLK_SCIF4 R8A7779_CLK_SCIF3
644+
R8A7779_CLK_SCIF2 R8A7779_CLK_SCIF1
645+
R8A7779_CLK_SCIF0 R8A7779_CLK_I2C3
646+
R8A7779_CLK_I2C2 R8A7779_CLK_I2C1
647+
R8A7779_CLK_I2C0
583648
>;
584649
clock-output-names =
585-
"hspi", "tmu2", "tmu1", "tmu0", "hscif1",
586-
"hscif0", "scif5", "scif4", "scif3", "scif2",
587-
"scif1", "scif0", "i2c3", "i2c2", "i2c1",
588-
"i2c0";
650+
"pwm", "hspi", "tmu2", "tmu1", "tmu0",
651+
"hscif1", "hscif0", "scif5", "scif4", "scif3",
652+
"scif2", "scif1", "scif0", "i2c3", "i2c2",
653+
"i2c1", "i2c0";
589654
};
590655
mstp1_clks: clocks@ffc80034 {
591656
compatible = "renesas,r8a7779-mstp-clocks",

‎arch/arm/boot/dts/r8a7790.dtsi‎

Lines changed: 81 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -376,6 +376,17 @@
376376
reg = <0 0xe6060000 0 0x250>;
377377
};
378378

379+
tpu: pwm@e60f0000 {
380+
compatible = "renesas,tpu-r8a7790", "renesas,tpu";
381+
reg = <0 0xe60f0000 0 0x148>;
382+
interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
383+
clocks = <&cpg CPG_MOD 304>;
384+
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
385+
resets = <&cpg 304>;
386+
#pwm-cells = <3>;
387+
status = "disabled";
388+
};
389+
379390
cpg: clock-controller@e6150000 {
380391
compatible = "renesas,r8a7790-cpg-mssr";
381392
reg = <0 0xe6150000 0 0x1000>;
@@ -1037,6 +1048,76 @@
10371048
status = "disabled";
10381049
};
10391050

1051+
pwm0: pwm@e6e30000 {
1052+
compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
1053+
reg = <0 0xe6e30000 0 0x8>;
1054+
clocks = <&cpg CPG_MOD 523>;
1055+
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1056+
resets = <&cpg 523>;
1057+
#pwm-cells = <2>;
1058+
status = "disabled";
1059+
};
1060+
1061+
pwm1: pwm@e6e31000 {
1062+
compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
1063+
reg = <0 0xe6e31000 0 0x8>;
1064+
clocks = <&cpg CPG_MOD 523>;
1065+
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1066+
resets = <&cpg 523>;
1067+
#pwm-cells = <2>;
1068+
status = "disabled";
1069+
};
1070+
1071+
pwm2: pwm@e6e32000 {
1072+
compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
1073+
reg = <0 0xe6e32000 0 0x8>;
1074+
clocks = <&cpg CPG_MOD 523>;
1075+
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1076+
resets = <&cpg 523>;
1077+
#pwm-cells = <2>;
1078+
status = "disabled";
1079+
};
1080+
1081+
pwm3: pwm@e6e33000 {
1082+
compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
1083+
reg = <0 0xe6e33000 0 0x8>;
1084+
clocks = <&cpg CPG_MOD 523>;
1085+
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1086+
resets = <&cpg 523>;
1087+
#pwm-cells = <2>;
1088+
status = "disabled";
1089+
};
1090+
1091+
pwm4: pwm@e6e34000 {
1092+
compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
1093+
reg = <0 0xe6e34000 0 0x8>;
1094+
clocks = <&cpg CPG_MOD 523>;
1095+
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1096+
resets = <&cpg 523>;
1097+
#pwm-cells = <2>;
1098+
status = "disabled";
1099+
};
1100+
1101+
pwm5: pwm@e6e35000 {
1102+
compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
1103+
reg = <0 0xe6e35000 0 0x8>;
1104+
clocks = <&cpg CPG_MOD 523>;
1105+
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1106+
resets = <&cpg 523>;
1107+
#pwm-cells = <2>;
1108+
status = "disabled";
1109+
};
1110+
1111+
pwm6: pwm@e6e36000 {
1112+
compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
1113+
reg = <0 0xe6e36000 0 0x8>;
1114+
clocks = <&cpg CPG_MOD 523>;
1115+
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1116+
resets = <&cpg 523>;
1117+
#pwm-cells = <2>;
1118+
status = "disabled";
1119+
};
1120+
10401121
can0: can@e6e80000 {
10411122
compatible = "renesas,can-r8a7790",
10421123
"renesas,rcar-gen2-can";

‎arch/arm64/boot/dts/renesas/Makefile‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -76,9 +76,11 @@ dtb-$(CONFIG_ARCH_R8A77961) += r8a779m3-ulcb-kf.dtb
7676
dtb-$(CONFIG_ARCH_R8A77965) += r8a779m5-salvator-xs.dtb
7777

7878
dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043u11-smarc.dtb
79+
dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043-smarc-pmod.dtbo
7980

8081
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc.dtb
8182
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc.dtb
83+
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc-cru-csi-ov5645.dtbo
8284

8385
dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-smarc.dtb
8486

‎arch/arm64/boot/dts/renesas/r8a779a0-falcon-csi-dsi.dtsi‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5,6 +5,8 @@
55
* Copyright (C) 2021 Glider bv
66
*/
77

8+
#include <dt-bindings/media/video-interfaces.h>
9+
810
&csi40 {
911
status = "okay";
1012

@@ -105,6 +107,7 @@
105107
port@4 {
106108
reg = <4>;
107109
max96712_out0: endpoint {
110+
bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
108111
clock-lanes = <0>;
109112
data-lanes = <1 2 3 4>;
110113
remote-endpoint = <&csi40_in>;
@@ -125,6 +128,7 @@
125128
port@4 {
126129
reg = <4>;
127130
max96712_out1: endpoint {
131+
bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
128132
clock-lanes = <0>;
129133
data-lanes = <1 2 3 4>;
130134
lane-polarities = <0 0 0 0 1>;
@@ -146,6 +150,7 @@
146150
port@4 {
147151
reg = <4>;
148152
max96712_out2: endpoint {
153+
bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
149154
clock-lanes = <0>;
150155
data-lanes = <1 2 3 4>;
151156
lane-polarities = <0 0 0 0 1>;

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