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| 1 | +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) |
| 2 | +# Copyright (c) 2025, Google LLC |
| 3 | +%YAML 1.2 |
| 4 | +--- |
| 5 | +$id: http://devicetree.org/schemas/usb/google,lga-dwc3.yaml# |
| 6 | +$schema: http://devicetree.org/meta-schemas/core.yaml# |
| 7 | + |
| 8 | +title: Google Tensor Series G5 (Laguna) DWC3 USB SoC Controller |
| 9 | + |
| 10 | +maintainers: |
| 11 | + - Roy Luo <royluo@google.com> |
| 12 | + |
| 13 | +description: |
| 14 | + Describes the DWC3 USB controller block implemented on Google Tensor SoCs, |
| 15 | + starting with the G5 generation (laguna). Based on Synopsys DWC3 IP, the |
| 16 | + controller features Dual-Role Device single port with hibernation add-on. |
| 17 | + |
| 18 | +properties: |
| 19 | + compatible: |
| 20 | + const: google,lga-dwc3 |
| 21 | + |
| 22 | + reg: |
| 23 | + items: |
| 24 | + - description: Core DWC3 IP registers. |
| 25 | + |
| 26 | + interrupts: |
| 27 | + items: |
| 28 | + - description: Core DWC3 interrupt. |
| 29 | + - description: High speed power management event for remote wakeup. |
| 30 | + - description: Super speed power management event for remote wakeup. |
| 31 | + |
| 32 | + interrupt-names: |
| 33 | + items: |
| 34 | + - const: core |
| 35 | + - const: hs_pme |
| 36 | + - const: ss_pme |
| 37 | + |
| 38 | + clocks: |
| 39 | + items: |
| 40 | + - description: Non-sticky module clock. |
| 41 | + - description: Sticky module clock. |
| 42 | + |
| 43 | + clock-names: |
| 44 | + items: |
| 45 | + - const: non_sticky |
| 46 | + - const: sticky |
| 47 | + |
| 48 | + resets: |
| 49 | + items: |
| 50 | + - description: Non-sticky module reset. |
| 51 | + - description: Sticky module reset. |
| 52 | + - description: DRD bus reset. |
| 53 | + - description: Top-level reset. |
| 54 | + |
| 55 | + reset-names: |
| 56 | + items: |
| 57 | + - const: non_sticky |
| 58 | + - const: sticky |
| 59 | + - const: drd_bus |
| 60 | + - const: top |
| 61 | + |
| 62 | + power-domains: |
| 63 | + items: |
| 64 | + - description: Power switchable domain, the child of top domain. |
| 65 | + Turning it on puts the controller into full power state, |
| 66 | + turning it off puts the controller into power gated state. |
| 67 | + - description: Top domain, the parent of power switchable domain. |
| 68 | + Turning it on puts the controller into power gated state, |
| 69 | + turning it off completely shuts off the controller. |
| 70 | + |
| 71 | + power-domain-names: |
| 72 | + items: |
| 73 | + - const: psw |
| 74 | + - const: top |
| 75 | + |
| 76 | + iommus: |
| 77 | + maxItems: 1 |
| 78 | + |
| 79 | + google,usb-cfg-csr: |
| 80 | + description: |
| 81 | + A phandle to a syscon node used to access the USB configuration |
| 82 | + registers. These registers are the top-level wrapper of the USB |
| 83 | + subsystem and provide control and status for the integrated USB |
| 84 | + controller and USB PHY. |
| 85 | + $ref: /schemas/types.yaml#/definitions/phandle-array |
| 86 | + items: |
| 87 | + - items: |
| 88 | + - description: phandle to the syscon node. |
| 89 | + - description: USB host controller configuration register offset. |
| 90 | + - description: USB custom interrrupts control register offset. |
| 91 | + |
| 92 | +required: |
| 93 | + - compatible |
| 94 | + - reg |
| 95 | + - interrupts |
| 96 | + - interrupt-names |
| 97 | + - clocks |
| 98 | + - clock-names |
| 99 | + - resets |
| 100 | + - reset-names |
| 101 | + - power-domains |
| 102 | + - power-domain-names |
| 103 | + - google,usb-cfg-csr |
| 104 | + |
| 105 | +allOf: |
| 106 | + - $ref: snps,dwc3-common.yaml# |
| 107 | + |
| 108 | +unevaluatedProperties: false |
| 109 | + |
| 110 | +examples: |
| 111 | + - | |
| 112 | + #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 113 | + #include <dt-bindings/interrupt-controller/irq.h> |
| 114 | + soc { |
| 115 | + #address-cells = <2>; |
| 116 | + #size-cells = <2>; |
| 117 | +
|
| 118 | + usb@c400000 { |
| 119 | + compatible = "google,lga-dwc3"; |
| 120 | + reg = <0 0x0c400000 0 0xd060>; |
| 121 | + interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH 0>, |
| 122 | + <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH 0>, |
| 123 | + <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH 0>; |
| 124 | + interrupt-names = "core", "hs_pme", "ss_pme"; |
| 125 | + clocks = <&hsion_usbc_non_sticky_clk>, <&hsion_usbc_sticky_clk>; |
| 126 | + clock-names = "non_sticky", "sticky"; |
| 127 | + resets = <&hsion_resets_usbc_non_sticky>, <&hsion_resets_usbc_sticky>, |
| 128 | + <&hsion_resets_usb_drd_bus>, <&hsion_resets_usb_top>; |
| 129 | + reset-names = "non_sticky", "sticky", "drd_bus", "top"; |
| 130 | + power-domains = <&hsio_n_usb_psw>, <&hsio_n_usb>; |
| 131 | + power-domain-names = "psw", "top"; |
| 132 | + phys = <&usb_phy 0>; |
| 133 | + phy-names = "usb2-phy"; |
| 134 | + snps,quirk-frame-length-adjustment = <0x20>; |
| 135 | + snps,gfladj-refclk-lpm-sel-quirk; |
| 136 | + snps,incr-burst-type-adjustment = <4>; |
| 137 | + google,usb-cfg-csr = <&usb_cfg_csr 0x0 0x20>; |
| 138 | + }; |
| 139 | + }; |
| 140 | +... |
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