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konradybciorobclark
konradybcio
authored and
robclark
committed
drm/msm/adreno: Add A702 support
The A702 is a weird mix of 600 and 700 series.. Perhaps even a testing ground for some A7xx features with good ol' A6xx silicon. It's basically A610 that's been beefed up with some new registers and hw features (like APRIV!), that was then cut back in size, memory bus and some other ways. Add support for it, tested with QCM2290 / RB1. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/579752/ Signed-off-by: Rob Clark <robdclark@chromium.org>
1 parent 77beba3 commit 1839751

3 files changed

Lines changed: 117 additions & 9 deletions

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‎drivers/gpu/drm/msm/adreno/a6xx_gpu.c‎

Lines changed: 84 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -837,6 +837,65 @@ const struct adreno_reglist a690_hwcg[] = {
837837
{}
838838
};
839839

840+
const struct adreno_reglist a702_hwcg[] = {
841+
{ REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222 },
842+
{ REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220 },
843+
{ REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000081 },
844+
{ REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf },
845+
{ REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222 },
846+
{ REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222 },
847+
{ REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222 },
848+
{ REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222 },
849+
{ REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111 },
850+
{ REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111 },
851+
{ REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111 },
852+
{ REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111 },
853+
{ REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777 },
854+
{ REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777 },
855+
{ REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777 },
856+
{ REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777 },
857+
{ REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222 },
858+
{ REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01202222 },
859+
{ REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220 },
860+
{ REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00 },
861+
{ REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05522022 },
862+
{ REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555 },
863+
{ REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011 },
864+
{ REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044 },
865+
{ REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222 },
866+
{ REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222 },
867+
{ REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222222 },
868+
{ REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002 },
869+
{ REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222 },
870+
{ REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000 },
871+
{ REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222 },
872+
{ REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200 },
873+
{ REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000 },
874+
{ REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000 },
875+
{ REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000 },
876+
{ REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004 },
877+
{ REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000 },
878+
{ REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222 },
879+
{ REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004 },
880+
{ REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002 },
881+
{ REG_A6XX_RBBM_ISDB_CNT, 0x00000182 },
882+
{ REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000 },
883+
{ REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000 },
884+
{ REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222 },
885+
{ REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111 },
886+
{ REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555 },
887+
{ REG_A6XX_RBBM_CLOCK_CNTL_FCHE, 0x00000222 },
888+
{ REG_A6XX_RBBM_CLOCK_DELAY_FCHE, 0x00000000 },
889+
{ REG_A6XX_RBBM_CLOCK_HYST_FCHE, 0x00000000 },
890+
{ REG_A6XX_RBBM_CLOCK_CNTL_GLC, 0x00222222 },
891+
{ REG_A6XX_RBBM_CLOCK_DELAY_GLC, 0x00000000 },
892+
{ REG_A6XX_RBBM_CLOCK_HYST_GLC, 0x00000000 },
893+
{ REG_A6XX_RBBM_CLOCK_CNTL_MHUB, 0x00000002 },
894+
{ REG_A6XX_RBBM_CLOCK_DELAY_MHUB, 0x00000000 },
895+
{ REG_A6XX_RBBM_CLOCK_HYST_MHUB, 0x00000000 },
896+
{}
897+
};
898+
840899
const struct adreno_reglist a730_hwcg[] = {
841900
{ REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222 },
842901
{ REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02022222 },
@@ -968,6 +1027,8 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
9681027
clock_cntl_on = 0x8aa8aa02;
9691028
else if (adreno_is_a610(adreno_gpu))
9701029
clock_cntl_on = 0xaaa8aa82;
1030+
else if (adreno_is_a702(adreno_gpu))
1031+
clock_cntl_on = 0xaaaaaa82;
9711032
else
9721033
clock_cntl_on = 0x8aa8aa82;
9731034

@@ -1008,14 +1069,14 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
10081069
return;
10091070

10101071
/* Disable SP clock before programming HWCG registers */
1011-
if (!adreno_is_a610(adreno_gpu) && !adreno_is_a7xx(adreno_gpu))
1072+
if (!adreno_is_a610_family(adreno_gpu) && !adreno_is_a7xx(adreno_gpu))
10121073
gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0);
10131074

10141075
for (i = 0; (reg = &adreno_gpu->info->hwcg[i], reg->offset); i++)
10151076
gpu_write(gpu, reg->offset, state ? reg->value : 0);
10161077

10171078
/* Enable SP clock */
1018-
if (!adreno_is_a610(adreno_gpu) && !adreno_is_a7xx(adreno_gpu))
1079+
if (!adreno_is_a610_family(adreno_gpu) && !adreno_is_a7xx(adreno_gpu))
10191080
gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1);
10201081

10211082
gpu_write(gpu, REG_A6XX_RBBM_CLOCK_CNTL, state ? clock_cntl_on : 0);
@@ -1243,7 +1304,7 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu)
12431304
const u32 *regs = a6xx_protect;
12441305
unsigned i, count, count_max;
12451306

1246-
if (adreno_is_a650(adreno_gpu)) {
1307+
if (adreno_is_a650(adreno_gpu) || adreno_is_a702(adreno_gpu)) {
12471308
regs = a650_protect;
12481309
count = ARRAY_SIZE(a650_protect);
12491310
count_max = 48;
@@ -1340,6 +1401,12 @@ static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
13401401
gpu->ubwc_config.rgb565_predicator = 1;
13411402
gpu->ubwc_config.uavflagprd_inv = 2;
13421403
}
1404+
1405+
if (adreno_is_a702(gpu)) {
1406+
gpu->ubwc_config.highest_bank_bit = 14;
1407+
gpu->ubwc_config.min_acc_len = 1;
1408+
gpu->ubwc_config.ubwc_mode = 2;
1409+
}
13431410
}
13441411

13451412
static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
@@ -1473,7 +1540,7 @@ static bool a6xx_ucode_check_version(struct a6xx_gpu *a6xx_gpu,
14731540
return false;
14741541

14751542
/* A7xx is safe! */
1476-
if (adreno_is_a7xx(adreno_gpu))
1543+
if (adreno_is_a7xx(adreno_gpu) || adreno_is_a702(adreno_gpu))
14771544
return true;
14781545

14791546
/*
@@ -1691,7 +1758,7 @@ static int hw_init(struct msm_gpu *gpu)
16911758
a6xx_set_hwcg(gpu, true);
16921759

16931760
/* VBIF/GBIF start*/
1694-
if (adreno_is_a610(adreno_gpu) ||
1761+
if (adreno_is_a610_family(adreno_gpu) ||
16951762
adreno_is_a640_family(adreno_gpu) ||
16961763
adreno_is_a650_family(adreno_gpu) ||
16971764
adreno_is_a7xx(adreno_gpu)) {
@@ -1725,6 +1792,7 @@ static int hw_init(struct msm_gpu *gpu)
17251792
}
17261793

17271794
if (!(adreno_is_a650_family(adreno_gpu) ||
1795+
adreno_is_a702(adreno_gpu) ||
17281796
adreno_is_a730(adreno_gpu))) {
17291797
gmem_range_min = adreno_is_a740_family(adreno_gpu) ? SZ_16M : SZ_1M;
17301798

@@ -1745,7 +1813,7 @@ static int hw_init(struct msm_gpu *gpu)
17451813
if (adreno_is_a640_family(adreno_gpu) || adreno_is_a650_family(adreno_gpu)) {
17461814
gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140);
17471815
gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c);
1748-
} else if (adreno_is_a610(adreno_gpu)) {
1816+
} else if (adreno_is_a610_family(adreno_gpu)) {
17491817
gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x00800060);
17501818
gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x40201b16);
17511819
} else if (!adreno_is_a7xx(adreno_gpu)) {
@@ -1760,13 +1828,18 @@ static int hw_init(struct msm_gpu *gpu)
17601828
if (adreno_is_a610(adreno_gpu)) {
17611829
gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 48);
17621830
gpu_write(gpu, REG_A6XX_CP_MEM_POOL_DBG_ADDR, 47);
1831+
} else if (adreno_is_a702(adreno_gpu)) {
1832+
gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 64);
1833+
gpu_write(gpu, REG_A6XX_CP_MEM_POOL_DBG_ADDR, 63);
17631834
} else if (!adreno_is_a7xx(adreno_gpu))
17641835
gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128);
17651836

17661837
/* Setting the primFifo thresholds default values,
17671838
* and vccCacheSkipDis=1 bit (0x200) for A640 and newer
17681839
*/
1769-
if (adreno_is_a690(adreno_gpu))
1840+
if (adreno_is_a702(adreno_gpu))
1841+
gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x0000c000);
1842+
else if (adreno_is_a690(adreno_gpu))
17701843
gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00800200);
17711844
else if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu))
17721845
gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200);
@@ -1806,7 +1879,7 @@ static int hw_init(struct msm_gpu *gpu)
18061879
gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x4fffff);
18071880
else if (adreno_is_a619(adreno_gpu))
18081881
gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x3fffff);
1809-
else if (adreno_is_a610(adreno_gpu))
1882+
else if (adreno_is_a610(adreno_gpu) || adreno_is_a702(adreno_gpu))
18101883
gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x3ffff);
18111884
else
18121885
gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x1fffff);
@@ -1842,6 +1915,9 @@ static int hw_init(struct msm_gpu *gpu)
18421915
else
18431916
gpu_write(gpu, REG_A6XX_CP_CHICKEN_DBG, 0x1);
18441917
gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x0);
1918+
} else if (adreno_is_a702(adreno_gpu)) {
1919+
/* Something to do with the HLSQ cluster */
1920+
gpu_write(gpu, REG_A6XX_CP_CHICKEN_DBG, BIT(24));
18451921
}
18461922

18471923
if (adreno_is_a690(adreno_gpu))

‎drivers/gpu/drm/msm/adreno/adreno_device.c‎

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -520,6 +520,24 @@ static const struct adreno_info gpulist[] = {
520520
.zapfw = "a690_zap.mdt",
521521
.hwcg = a690_hwcg,
522522
.address_space_size = SZ_16G,
523+
}, {
524+
.chip_ids = ADRENO_CHIP_IDS(0x07000200),
525+
.family = ADRENO_6XX_GEN1, /* NOT a mistake! */
526+
.fw = {
527+
[ADRENO_FW_SQE] = "a702_sqe.fw",
528+
},
529+
.gmem = SZ_128K,
530+
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
531+
.quirks = ADRENO_QUIRK_HAS_HW_APRIV,
532+
.init = a6xx_gpu_init,
533+
.zapfw = "a702_zap.mbn",
534+
.hwcg = a702_hwcg,
535+
.speedbins = ADRENO_SPEEDBINS(
536+
{ 0, 0 },
537+
{ 236, 1 },
538+
{ 178, 2 },
539+
{ 142, 3 },
540+
),
523541
}, {
524542
.chip_ids = ADRENO_CHIP_IDS(0x07030001),
525543
.family = ADRENO_7XX_GEN1,

‎drivers/gpu/drm/msm/adreno/adreno_gpu.h‎

Lines changed: 15 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -78,7 +78,7 @@ struct adreno_reglist {
7878
};
7979

8080
extern const struct adreno_reglist a612_hwcg[], a615_hwcg[], a630_hwcg[], a640_hwcg[], a650_hwcg[];
81-
extern const struct adreno_reglist a660_hwcg[], a690_hwcg[], a730_hwcg[], a740_hwcg[];
81+
extern const struct adreno_reglist a660_hwcg[], a690_hwcg[], a702_hwcg[], a730_hwcg[], a740_hwcg[];
8282

8383
struct adreno_speedbin {
8484
uint16_t fuse;
@@ -388,6 +388,20 @@ static inline int adreno_is_a690(const struct adreno_gpu *gpu)
388388
return gpu->info->chip_ids[0] == 0x06090000;
389389
}
390390

391+
static inline int adreno_is_a702(const struct adreno_gpu *gpu)
392+
{
393+
return gpu->info->chip_ids[0] == 0x07000200;
394+
}
395+
396+
static inline int adreno_is_a610_family(const struct adreno_gpu *gpu)
397+
{
398+
if (WARN_ON_ONCE(!gpu->info))
399+
return false;
400+
401+
/* TODO: A612 */
402+
return adreno_is_a610(gpu) || adreno_is_a702(gpu);
403+
}
404+
391405
/* check for a615, a616, a618, a619 or any a630 derivatives */
392406
static inline int adreno_is_a630_family(const struct adreno_gpu *gpu)
393407
{

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