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Vladimir Lypakbebarino
Vladimir Lypak
authored and
bebarino
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dt-bindings: clock: add Qualcomm MSM8953 GCC driver bindings
Add bindings and compatible to document MSM8953 GCC (Global Clock Controller) driver. Signed-off-by: Vladimir Lypak <junak.pub@gmail.com> Signed-off-by: Adam Skladowski <a_skl39@protonmail.com> Signed-off-by: Sireesh Kodali <sireeshkodali@protonmail.com> Link: https://lore.kernel.org/r/Q6uB3NRxqtD8Prsmliv8ZdsTXGeviv7lb2jQ743jr1E@cp4-web-036.plabs.ch Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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‎Documentation/devicetree/bindings/clock/qcom,gcc.yaml‎

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- dt-bindings/clock/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
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- dt-bindings/reset/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
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- dt-bindings/clock/qcom,gcc-msm8939.h
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- dt-bindings/clock/qcom,gcc-msm8953.h
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- dt-bindings/reset/qcom,gcc-msm8939.h
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- dt-bindings/clock/qcom,gcc-msm8660.h
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- dt-bindings/reset/qcom,gcc-msm8660.h
@@ -46,6 +47,7 @@ properties:
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- qcom,gcc-msm8660
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- qcom,gcc-msm8916
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- qcom,gcc-msm8939
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- qcom,gcc-msm8953
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- qcom,gcc-msm8960
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- qcom,gcc-msm8974
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- qcom,gcc-msm8974pro

‎include/dt-bindings/clock/qcom,gcc-msm8953.h‎

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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#ifndef _DT_BINDINGS_CLK_MSM_GCC_8953_H
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#define _DT_BINDINGS_CLK_MSM_GCC_8953_H
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/* Clocks */
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#define APC0_DROOP_DETECTOR_CLK_SRC 0
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#define APC1_DROOP_DETECTOR_CLK_SRC 1
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#define APSS_AHB_CLK_SRC 2
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#define BLSP1_QUP1_I2C_APPS_CLK_SRC 3
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#define BLSP1_QUP1_SPI_APPS_CLK_SRC 4
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#define BLSP1_QUP2_I2C_APPS_CLK_SRC 5
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#define BLSP1_QUP2_SPI_APPS_CLK_SRC 6
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#define BLSP1_QUP3_I2C_APPS_CLK_SRC 7
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#define BLSP1_QUP3_SPI_APPS_CLK_SRC 8
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#define BLSP1_QUP4_I2C_APPS_CLK_SRC 9
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#define BLSP1_QUP4_SPI_APPS_CLK_SRC 10
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#define BLSP1_UART1_APPS_CLK_SRC 11
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#define BLSP1_UART2_APPS_CLK_SRC 12
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#define BLSP2_QUP1_I2C_APPS_CLK_SRC 13
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#define BLSP2_QUP1_SPI_APPS_CLK_SRC 14
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#define BLSP2_QUP2_I2C_APPS_CLK_SRC 15
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#define BLSP2_QUP2_SPI_APPS_CLK_SRC 16
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#define BLSP2_QUP3_I2C_APPS_CLK_SRC 17
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#define BLSP2_QUP3_SPI_APPS_CLK_SRC 18
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#define BLSP2_QUP4_I2C_APPS_CLK_SRC 19
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#define BLSP2_QUP4_SPI_APPS_CLK_SRC 20
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#define BLSP2_UART1_APPS_CLK_SRC 21
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#define BLSP2_UART2_APPS_CLK_SRC 22
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#define BYTE0_CLK_SRC 23
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#define BYTE1_CLK_SRC 24
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#define CAMSS_GP0_CLK_SRC 25
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#define CAMSS_GP1_CLK_SRC 26
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#define CAMSS_TOP_AHB_CLK_SRC 27
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#define CCI_CLK_SRC 28
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#define CPP_CLK_SRC 29
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#define CRYPTO_CLK_SRC 30
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#define CSI0PHYTIMER_CLK_SRC 31
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#define CSI0P_CLK_SRC 32
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#define CSI0_CLK_SRC 33
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#define CSI1PHYTIMER_CLK_SRC 34
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#define CSI1P_CLK_SRC 35
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#define CSI1_CLK_SRC 36
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#define CSI2PHYTIMER_CLK_SRC 37
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#define CSI2P_CLK_SRC 38
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#define CSI2_CLK_SRC 39
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#define ESC0_CLK_SRC 40
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#define ESC1_CLK_SRC 41
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#define GCC_APC0_DROOP_DETECTOR_GPLL0_CLK 42
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#define GCC_APC1_DROOP_DETECTOR_GPLL0_CLK 43
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#define GCC_APSS_AHB_CLK 44
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#define GCC_APSS_AXI_CLK 45
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#define GCC_APSS_TCU_ASYNC_CLK 46
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#define GCC_BIMC_GFX_CLK 47
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#define GCC_BIMC_GPU_CLK 48
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#define GCC_BLSP1_AHB_CLK 49
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#define GCC_BLSP1_QUP1_I2C_APPS_CLK 50
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#define GCC_BLSP1_QUP1_SPI_APPS_CLK 51
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#define GCC_BLSP1_QUP2_I2C_APPS_CLK 52
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#define GCC_BLSP1_QUP2_SPI_APPS_CLK 53
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#define GCC_BLSP1_QUP3_I2C_APPS_CLK 54
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#define GCC_BLSP1_QUP3_SPI_APPS_CLK 55
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#define GCC_BLSP1_QUP4_I2C_APPS_CLK 56
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#define GCC_BLSP1_QUP4_SPI_APPS_CLK 57
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#define GCC_BLSP1_UART1_APPS_CLK 58
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#define GCC_BLSP1_UART2_APPS_CLK 59
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#define GCC_BLSP2_AHB_CLK 60
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#define GCC_BLSP2_QUP1_I2C_APPS_CLK 61
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#define GCC_BLSP2_QUP1_SPI_APPS_CLK 62
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#define GCC_BLSP2_QUP2_I2C_APPS_CLK 63
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#define GCC_BLSP2_QUP2_SPI_APPS_CLK 64
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#define GCC_BLSP2_QUP3_I2C_APPS_CLK 65
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#define GCC_BLSP2_QUP3_SPI_APPS_CLK 66
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#define GCC_BLSP2_QUP4_I2C_APPS_CLK 67
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#define GCC_BLSP2_QUP4_SPI_APPS_CLK 68
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#define GCC_BLSP2_UART1_APPS_CLK 69
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#define GCC_BLSP2_UART2_APPS_CLK 70
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#define GCC_BOOT_ROM_AHB_CLK 71
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#define GCC_CAMSS_AHB_CLK 72
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#define GCC_CAMSS_CCI_AHB_CLK 73
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#define GCC_CAMSS_CCI_CLK 74
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#define GCC_CAMSS_CPP_AHB_CLK 75
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#define GCC_CAMSS_CPP_AXI_CLK 76
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#define GCC_CAMSS_CPP_CLK 77
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#define GCC_CAMSS_CSI0PHYTIMER_CLK 78
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#define GCC_CAMSS_CSI0PHY_CLK 79
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#define GCC_CAMSS_CSI0PIX_CLK 80
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#define GCC_CAMSS_CSI0RDI_CLK 81
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#define GCC_CAMSS_CSI0_AHB_CLK 82
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#define GCC_CAMSS_CSI0_CLK 83
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#define GCC_CAMSS_CSI0_CSIPHY_3P_CLK 84
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#define GCC_CAMSS_CSI1PHYTIMER_CLK 85
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#define GCC_CAMSS_CSI1PHY_CLK 86
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#define GCC_CAMSS_CSI1PIX_CLK 87
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#define GCC_CAMSS_CSI1RDI_CLK 88
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#define GCC_CAMSS_CSI1_AHB_CLK 89
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#define GCC_CAMSS_CSI1_CLK 90
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#define GCC_CAMSS_CSI1_CSIPHY_3P_CLK 91
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#define GCC_CAMSS_CSI2PHYTIMER_CLK 92
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#define GCC_CAMSS_CSI2PHY_CLK 93
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#define GCC_CAMSS_CSI2PIX_CLK 94
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#define GCC_CAMSS_CSI2RDI_CLK 95
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#define GCC_CAMSS_CSI2_AHB_CLK 96
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#define GCC_CAMSS_CSI2_CLK 97
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#define GCC_CAMSS_CSI2_CSIPHY_3P_CLK 98
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#define GCC_CAMSS_CSI_VFE0_CLK 99
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#define GCC_CAMSS_CSI_VFE1_CLK 100
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#define GCC_CAMSS_GP0_CLK 101
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#define GCC_CAMSS_GP1_CLK 102
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#define GCC_CAMSS_ISPIF_AHB_CLK 103
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#define GCC_CAMSS_JPEG0_CLK 104
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#define GCC_CAMSS_JPEG_AHB_CLK 105
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#define GCC_CAMSS_JPEG_AXI_CLK 106
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#define GCC_CAMSS_MCLK0_CLK 107
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#define GCC_CAMSS_MCLK1_CLK 108
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#define GCC_CAMSS_MCLK2_CLK 109
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#define GCC_CAMSS_MCLK3_CLK 110
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#define GCC_CAMSS_MICRO_AHB_CLK 111
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#define GCC_CAMSS_TOP_AHB_CLK 112
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#define GCC_CAMSS_VFE0_AHB_CLK 113
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#define GCC_CAMSS_VFE0_AXI_CLK 114
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#define GCC_CAMSS_VFE0_CLK 115
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#define GCC_CAMSS_VFE1_AHB_CLK 116
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#define GCC_CAMSS_VFE1_AXI_CLK 117
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#define GCC_CAMSS_VFE1_CLK 118
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#define GCC_CPP_TBU_CLK 119
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#define GCC_CRYPTO_AHB_CLK 120
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#define GCC_CRYPTO_AXI_CLK 121
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#define GCC_CRYPTO_CLK 122
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#define GCC_DCC_CLK 123
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#define GCC_GP1_CLK 124
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#define GCC_GP2_CLK 125
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#define GCC_GP3_CLK 126
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#define GCC_JPEG_TBU_CLK 127
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#define GCC_MDP_TBU_CLK 128
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#define GCC_MDSS_AHB_CLK 129
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#define GCC_MDSS_AXI_CLK 130
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#define GCC_MDSS_BYTE0_CLK 131
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#define GCC_MDSS_BYTE1_CLK 132
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#define GCC_MDSS_ESC0_CLK 133
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#define GCC_MDSS_ESC1_CLK 134
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#define GCC_MDSS_MDP_CLK 135
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#define GCC_MDSS_PCLK0_CLK 136
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#define GCC_MDSS_PCLK1_CLK 137
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#define GCC_MDSS_VSYNC_CLK 138
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#define GCC_MSS_CFG_AHB_CLK 139
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#define GCC_MSS_Q6_BIMC_AXI_CLK 140
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#define GCC_OXILI_AHB_CLK 141
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#define GCC_OXILI_AON_CLK 142
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#define GCC_OXILI_GFX3D_CLK 143
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#define GCC_OXILI_TIMER_CLK 144
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#define GCC_PCNOC_USB3_AXI_CLK 145
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#define GCC_PDM2_CLK 146
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#define GCC_PDM_AHB_CLK 147
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#define GCC_PRNG_AHB_CLK 148
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#define GCC_QDSS_DAP_CLK 149
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#define GCC_QUSB_REF_CLK 150
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#define GCC_RBCPR_GFX_CLK 151
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#define GCC_SDCC1_AHB_CLK 152
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#define GCC_SDCC1_APPS_CLK 153
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#define GCC_SDCC1_ICE_CORE_CLK 154
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#define GCC_SDCC2_AHB_CLK 155
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#define GCC_SDCC2_APPS_CLK 156
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#define GCC_SMMU_CFG_CLK 157
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#define GCC_USB30_MASTER_CLK 158
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#define GCC_USB30_MOCK_UTMI_CLK 159
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#define GCC_USB30_SLEEP_CLK 160
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#define GCC_USB3_AUX_CLK 161
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#define GCC_USB3_PIPE_CLK 162
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#define GCC_USB_PHY_CFG_AHB_CLK 163
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#define GCC_USB_SS_REF_CLK 164
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#define GCC_VENUS0_AHB_CLK 165
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#define GCC_VENUS0_AXI_CLK 166
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#define GCC_VENUS0_CORE0_VCODEC0_CLK 167
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#define GCC_VENUS0_VCODEC0_CLK 168
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#define GCC_VENUS_TBU_CLK 169
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#define GCC_VFE1_TBU_CLK 170
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#define GCC_VFE_TBU_CLK 171
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#define GFX3D_CLK_SRC 172
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#define GP1_CLK_SRC 173
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#define GP2_CLK_SRC 174
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#define GP3_CLK_SRC 175
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#define GPLL0 176
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#define GPLL0_EARLY 177
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#define GPLL2 178
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#define GPLL2_EARLY 179
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#define GPLL3 180
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#define GPLL3_EARLY 181
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#define GPLL4 182
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#define GPLL4_EARLY 183
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#define GPLL6 184
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#define GPLL6_EARLY 185
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#define JPEG0_CLK_SRC 186
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#define MCLK0_CLK_SRC 187
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#define MCLK1_CLK_SRC 188
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#define MCLK2_CLK_SRC 189
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#define MCLK3_CLK_SRC 190
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#define MDP_CLK_SRC 191
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#define PCLK0_CLK_SRC 192
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#define PCLK1_CLK_SRC 193
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#define PDM2_CLK_SRC 194
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#define RBCPR_GFX_CLK_SRC 195
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#define SDCC1_APPS_CLK_SRC 196
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#define SDCC1_ICE_CORE_CLK_SRC 197
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#define SDCC2_APPS_CLK_SRC 198
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#define USB30_MASTER_CLK_SRC 199
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#define USB30_MOCK_UTMI_CLK_SRC 200
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#define USB3_AUX_CLK_SRC 201
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#define VCODEC0_CLK_SRC 202
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#define VFE0_CLK_SRC 203
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#define VFE1_CLK_SRC 204
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#define VSYNC_CLK_SRC 205
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/* GCC block resets */
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#define GCC_CAMSS_MICRO_BCR 0
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#define GCC_MSS_BCR 1
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#define GCC_QUSB2_PHY_BCR 2
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#define GCC_USB3PHY_PHY_BCR 3
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#define GCC_USB3_PHY_BCR 4
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#define GCC_USB_30_BCR 5
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/* GDSCs */
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#define CPP_GDSC 0
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#define JPEG_GDSC 1
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#define MDSS_GDSC 2
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#define OXILI_CX_GDSC 3
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#define OXILI_GX_GDSC 4
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#define USB30_GDSC 5
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#define VENUS_CORE0_GDSC 6
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#define VENUS_GDSC 7
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#define VFE0_GDSC 8
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#define VFE1_GDSC 9
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#endif

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