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Linus Walleij
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Merge tag 'samsung-pinctrl-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel
Samsung pinctrl drivers changes for v6.19 Add pin controller support for Samsung Exynos8890 and Axis ARTPEC-9 SoCs. The latter is a newer design of Artpec SoCs made/designed by Samsung, thus it shares most of the core blocks with Samsung Exynos, including the pinctrl. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2 parents ea2bfb8 + 3cfc60e commit 1d80a68

5 files changed

Lines changed: 218 additions & 1 deletion

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‎Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -41,6 +41,7 @@ properties:
4141
- samsung,exynos7870-wakeup-eint
4242
- samsung,exynos7885-wakeup-eint
4343
- samsung,exynos850-wakeup-eint
44+
- samsung,exynos8890-wakeup-eint
4445
- samsung,exynos8895-wakeup-eint
4546
- const: samsung,exynos7-wakeup-eint
4647
- items:

‎Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml‎

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -36,6 +36,7 @@ properties:
3636
compatible:
3737
enum:
3838
- axis,artpec8-pinctrl
39+
- axis,artpec9-pinctrl
3940
- google,gs101-pinctrl
4041
- samsung,s3c64xx-pinctrl
4142
- samsung,s5pv210-pinctrl
@@ -52,6 +53,7 @@ properties:
5253
- samsung,exynos7870-pinctrl
5354
- samsung,exynos7885-pinctrl
5455
- samsung,exynos850-pinctrl
56+
- samsung,exynos8890-pinctrl
5557
- samsung,exynos8895-pinctrl
5658
- samsung,exynos9810-pinctrl
5759
- samsung,exynos990-pinctrl
@@ -133,7 +135,9 @@ allOf:
133135
properties:
134136
compatible:
135137
contains:
136-
const: google,gs101-pinctrl
138+
enum:
139+
- google,gs101-pinctrl
140+
- samsung,exynos8890-pinctrl
137141
then:
138142
required:
139143
- clocks

‎drivers/pinctrl/samsung/pinctrl-exynos-arm64.c‎

Lines changed: 206 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1485,6 +1485,163 @@ const struct samsung_pinctrl_of_match_data exynosautov920_of_data __initconst =
14851485
.num_ctrl = ARRAY_SIZE(exynosautov920_pin_ctrl),
14861486
};
14871487

1488+
/* pin banks of exynos8890 pin-controller 0 (ALIVE) */
1489+
static const struct samsung_pin_bank_data exynos8890_pin_banks0[] __initconst = {
1490+
/* Must start with EINTG banks, ordered by EINT group number. */
1491+
EXYNOS7870_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
1492+
EXYNOS7870_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),
1493+
EXYNOS7870_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),
1494+
EXYNOS7870_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c),
1495+
};
1496+
1497+
/* pin banks of exynos8890 pin-controller 1 (AUD) */
1498+
static const struct samsung_pin_bank_data exynos8890_pin_banks1[] __initconst = {
1499+
/* Must start with EINTG banks, ordered by EINT group number. */
1500+
EXYNOS8895_PIN_BANK_EINTG(7, 0x000, "gph0", 0x00),
1501+
};
1502+
1503+
/* pin banks of exynos8890 pin-controller 2 (CCORE) */
1504+
static const struct samsung_pin_bank_data exynos8890_pin_banks2[] __initconst = {
1505+
/* Must start with EINTG banks, ordered by EINT group number. */
1506+
EXYNOS8895_PIN_BANK_EINTG(2, 0x000, "etc0", 0x00),
1507+
};
1508+
1509+
/* pin banks of exynos8890 pin-controller 3 (ESE) */
1510+
static const struct samsung_pin_bank_data exynos8890_pin_banks3[] __initconst = {
1511+
/* Must start with EINTG banks, ordered by EINT group number. */
1512+
EXYNOS8895_PIN_BANK_EINTG(5, 0x000, "gpf3", 0x00),
1513+
};
1514+
1515+
/* pin banks of exynos8890 pin-controller 4 (FP) */
1516+
static const struct samsung_pin_bank_data exynos8890_pin_banks4[] __initconst = {
1517+
/* Must start with EINTG banks, ordered by EINT group number. */
1518+
EXYNOS8895_PIN_BANK_EINTG(4, 0x000, "gpf2", 0x00),
1519+
};
1520+
1521+
/* pin banks of exynos8890 pin-controller 5 (FSYS0) */
1522+
static const struct samsung_pin_bank_data exynos8890_pin_banks5[] __initconst = {
1523+
/* Must start with EINTG banks, ordered by EINT group number. */
1524+
EXYNOS8895_PIN_BANK_EINTG(4, 0x000, "gpi1", 0x00),
1525+
EXYNOS8895_PIN_BANK_EINTG(8, 0x020, "gpi2", 0x04),
1526+
};
1527+
1528+
/* pin banks of exynos8890 pin-controller 6 (FSYS1) */
1529+
static const struct samsung_pin_bank_data exynos8890_pin_banks6[] __initconst = {
1530+
/* Must start with EINTG banks, ordered by EINT group number. */
1531+
EXYNOS8895_PIN_BANK_EINTG(7, 0x000, "gpj0", 0x00),
1532+
};
1533+
1534+
/* pin banks of exynos8890 pin-controller 7 (NFC) */
1535+
static const struct samsung_pin_bank_data exynos8890_pin_banks7[] __initconst = {
1536+
/* Must start with EINTG banks, ordered by EINT group number. */
1537+
EXYNOS8895_PIN_BANK_EINTG(3, 0x000, "gpf0", 0x00),
1538+
};
1539+
1540+
/* pin banks of exynos8890 pin-controller 8 (PERIC0) */
1541+
static const struct samsung_pin_bank_data exynos8890_pin_banks8[] __initconst = {
1542+
/* Must start with EINTG banks, ordered by EINT group number. */
1543+
EXYNOS8895_PIN_BANK_EINTG(6, 0x000, "gpi0", 0x00),
1544+
EXYNOS8895_PIN_BANK_EINTG(8, 0x020, "gpd0", 0x04),
1545+
EXYNOS8895_PIN_BANK_EINTG(6, 0x040, "gpd1", 0x08),
1546+
EXYNOS8895_PIN_BANK_EINTG(4, 0x060, "gpd2", 0x0c),
1547+
EXYNOS8895_PIN_BANK_EINTG(4, 0x080, "gpd3", 0x10),
1548+
EXYNOS8895_PIN_BANK_EINTG(2, 0x0A0, "gpb1", 0x14),
1549+
EXYNOS8895_PIN_BANK_EINTG(2, 0x0C0, "gpb2", 0x18),
1550+
EXYNOS8895_PIN_BANK_EINTG(3, 0x0E0, "gpb0", 0x1c),
1551+
EXYNOS8895_PIN_BANK_EINTG(5, 0x100, "gpc0", 0x20),
1552+
EXYNOS8895_PIN_BANK_EINTG(5, 0x120, "gpc1", 0x24),
1553+
EXYNOS8895_PIN_BANK_EINTG(6, 0x140, "gpc2", 0x28),
1554+
EXYNOS8895_PIN_BANK_EINTG(8, 0x160, "gpc3", 0x2c),
1555+
EXYNOS8895_PIN_BANK_EINTG(4, 0x180, "gpk0", 0x30),
1556+
EXYNOS8895_PIN_BANK_EINTG(7, 0x1A0, "etc1", 0x34),
1557+
};
1558+
1559+
/* pin banks of exynos8890 pin-controller 9 (PERIC1) */
1560+
static const struct samsung_pin_bank_data exynos8890_pin_banks9[] __initconst = {
1561+
/* Must start with EINTG banks, ordered by EINT group number. */
1562+
EXYNOS8895_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00),
1563+
EXYNOS8895_PIN_BANK_EINTG(8, 0x020, "gpe5", 0x04),
1564+
EXYNOS8895_PIN_BANK_EINTG(8, 0x040, "gpe6", 0x08),
1565+
EXYNOS8895_PIN_BANK_EINTG(8, 0x060, "gpj1", 0x0c),
1566+
EXYNOS8895_PIN_BANK_EINTG(2, 0x080, "gpj2", 0x10),
1567+
EXYNOS8895_PIN_BANK_EINTG(8, 0x0A0, "gpe2", 0x14),
1568+
EXYNOS8895_PIN_BANK_EINTG(8, 0x0C0, "gpe3", 0x18),
1569+
EXYNOS8895_PIN_BANK_EINTG(8, 0x0E0, "gpe4", 0x1c),
1570+
EXYNOS8895_PIN_BANK_EINTG(8, 0x100, "gpe1", 0x20),
1571+
EXYNOS8895_PIN_BANK_EINTG(4, 0x120, "gpe7", 0x24),
1572+
EXYNOS8895_PIN_BANK_EINTG(3, 0x140, "gpg0", 0x28),
1573+
};
1574+
1575+
/* pin banks of exynos8890 pin-controller 10 (TOUCH) */
1576+
static const struct samsung_pin_bank_data exynos8890_pin_banks10[] __initconst = {
1577+
/* Must start with EINTG banks, ordered by EINT group number. */
1578+
EXYNOS8895_PIN_BANK_EINTG(3, 0x000, "gpf1", 0x00),
1579+
};
1580+
1581+
static const struct samsung_pin_ctrl exynos8890_pin_ctrl[] __initconst = {
1582+
{
1583+
/* pin-controller instance 0 Alive data */
1584+
.pin_banks = exynos8890_pin_banks0,
1585+
.nr_banks = ARRAY_SIZE(exynos8890_pin_banks0),
1586+
.eint_wkup_init = exynos_eint_wkup_init,
1587+
}, {
1588+
/* pin-controller instance 1 AUD data */
1589+
.pin_banks = exynos8890_pin_banks1,
1590+
.nr_banks = ARRAY_SIZE(exynos8890_pin_banks1),
1591+
.eint_gpio_init = exynos_eint_gpio_init,
1592+
}, {
1593+
/* pin-controller instance 2 CCORE data */
1594+
.pin_banks = exynos8890_pin_banks2,
1595+
.nr_banks = ARRAY_SIZE(exynos8890_pin_banks2),
1596+
.eint_gpio_init = exynos_eint_gpio_init,
1597+
}, {
1598+
/* pin-controller instance 3 ESE data */
1599+
.pin_banks = exynos8890_pin_banks3,
1600+
.nr_banks = ARRAY_SIZE(exynos8890_pin_banks3),
1601+
.eint_gpio_init = exynos_eint_gpio_init,
1602+
}, {
1603+
/* pin-controller instance 4 FP data */
1604+
.pin_banks = exynos8890_pin_banks4,
1605+
.nr_banks = ARRAY_SIZE(exynos8890_pin_banks4),
1606+
.eint_gpio_init = exynos_eint_gpio_init,
1607+
}, {
1608+
/* pin-controller instance 5 FSYS0 data */
1609+
.pin_banks = exynos8890_pin_banks5,
1610+
.nr_banks = ARRAY_SIZE(exynos8890_pin_banks5),
1611+
.eint_gpio_init = exynos_eint_gpio_init,
1612+
}, {
1613+
/* pin-controller instance 6 FSYS1 data */
1614+
.pin_banks = exynos8890_pin_banks6,
1615+
.nr_banks = ARRAY_SIZE(exynos8890_pin_banks6),
1616+
.eint_gpio_init = exynos_eint_gpio_init,
1617+
}, {
1618+
/* pin-controller instance 7 NFC data */
1619+
.pin_banks = exynos8890_pin_banks7,
1620+
.nr_banks = ARRAY_SIZE(exynos8890_pin_banks7),
1621+
.eint_gpio_init = exynos_eint_gpio_init,
1622+
}, {
1623+
/* pin-controller instance 8 PERIC0 data */
1624+
.pin_banks = exynos8890_pin_banks8,
1625+
.nr_banks = ARRAY_SIZE(exynos8890_pin_banks8),
1626+
.eint_gpio_init = exynos_eint_gpio_init,
1627+
}, {
1628+
/* pin-controller instance 9 PERIC1 data */
1629+
.pin_banks = exynos8890_pin_banks9,
1630+
.nr_banks = ARRAY_SIZE(exynos8890_pin_banks9),
1631+
.eint_gpio_init = exynos_eint_gpio_init,
1632+
}, {
1633+
/* pin-controller instance 10 TOUCH data */
1634+
.pin_banks = exynos8890_pin_banks10,
1635+
.nr_banks = ARRAY_SIZE(exynos8890_pin_banks10),
1636+
.eint_gpio_init = exynos_eint_gpio_init,
1637+
},
1638+
};
1639+
1640+
const struct samsung_pinctrl_of_match_data exynos8890_of_data __initconst = {
1641+
.ctrl = exynos8890_pin_ctrl,
1642+
.num_ctrl = ARRAY_SIZE(exynos8890_pin_ctrl),
1643+
};
1644+
14881645
/* pin banks of exynos8895 pin-controller 0 (ALIVE) */
14891646
static const struct samsung_pin_bank_data exynos8895_pin_banks0[] __initconst = {
14901647
EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa0", 0x00),
@@ -1866,3 +2023,52 @@ const struct samsung_pinctrl_of_match_data artpec8_of_data __initconst = {
18662023
.ctrl = artpec8_pin_ctrl,
18672024
.num_ctrl = ARRAY_SIZE(artpec8_pin_ctrl),
18682025
};
2026+
2027+
/* pin banks of artpec9 pin-controller (FSYS0) */
2028+
static const struct samsung_pin_bank_data artpec9_pin_banks0[] __initconst = {
2029+
ARTPEC_PIN_BANK_EINTG(8, 0x000, "gpf0", 0x00),
2030+
ARTPEC_PIN_BANK_EINTG(8, 0x020, "gpf1", 0x04),
2031+
ARTPEC_PIN_BANK_EINTG(8, 0x040, "gpe0", 0x08),
2032+
ARTPEC_PIN_BANK_EINTG(8, 0x060, "gpe1", 0x0c),
2033+
ARTPEC_PIN_BANK_EINTG(8, 0x080, "gpe2", 0x10),
2034+
ARTPEC_PIN_BANK_EINTG(8, 0x0a0, "gpe3", 0x14),
2035+
ARTPEC_PIN_BANK_EINTG(2, 0x0c0, "gpe4", 0x18),
2036+
ARTPEC_PIN_BANK_EINTG(8, 0x0e0, "gps0", 0x1c),
2037+
ARTPEC_PIN_BANK_EINTG(8, 0x100, "gps1", 0x20),
2038+
ARTPEC_PIN_BANK_EINTG(5, 0x120, "gpi0", 0x24),
2039+
};
2040+
2041+
/* pin banks of artpec9 pin-controller (FSYS1) */
2042+
static const struct samsung_pin_bank_data artpec9_pin_banks1[] __initconst = {
2043+
ARTPEC_PIN_BANK_EINTG(2, 0x000, "gpu0", 0x00),
2044+
};
2045+
2046+
/* pin banks of artpec9 pin-controller (PERIC) */
2047+
static const struct samsung_pin_bank_data artpec9_pin_banks2[] __initconst = {
2048+
ARTPEC_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
2049+
ARTPEC_PIN_BANK_EINTG(8, 0x020, "gpa1", 0x04),
2050+
};
2051+
2052+
static const struct samsung_pin_ctrl artpec9_pin_ctrl[] __initconst = {
2053+
{
2054+
/* pin-controller instance 0 FSYS0 data */
2055+
.pin_banks = artpec9_pin_banks0,
2056+
.nr_banks = ARRAY_SIZE(artpec9_pin_banks0),
2057+
.eint_gpio_init = exynos_eint_gpio_init,
2058+
}, {
2059+
/* pin-controller instance 1 FSYS1 data */
2060+
.pin_banks = artpec9_pin_banks1,
2061+
.nr_banks = ARRAY_SIZE(artpec9_pin_banks1),
2062+
.eint_gpio_init = exynos_eint_gpio_init,
2063+
}, {
2064+
/* pin-controller instance 2 PERIC data */
2065+
.pin_banks = artpec9_pin_banks2,
2066+
.nr_banks = ARRAY_SIZE(artpec9_pin_banks2),
2067+
.eint_gpio_init = exynos_eint_gpio_init,
2068+
},
2069+
};
2070+
2071+
const struct samsung_pinctrl_of_match_data artpec9_of_data __initconst = {
2072+
.ctrl = artpec9_pin_ctrl,
2073+
.num_ctrl = ARRAY_SIZE(artpec9_pin_ctrl),
2074+
};

‎drivers/pinctrl/samsung/pinctrl-samsung.c‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1484,6 +1484,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = {
14841484
#ifdef CONFIG_PINCTRL_EXYNOS_ARM64
14851485
{ .compatible = "axis,artpec8-pinctrl",
14861486
.data = &artpec8_of_data },
1487+
{ .compatible = "axis,artpec9-pinctrl",
1488+
.data = &artpec9_of_data },
14871489
{ .compatible = "google,gs101-pinctrl",
14881490
.data = &gs101_of_data },
14891491
{ .compatible = "samsung,exynos2200-pinctrl",
@@ -1498,6 +1500,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = {
14981500
.data = &exynos7885_of_data },
14991501
{ .compatible = "samsung,exynos850-pinctrl",
15001502
.data = &exynos850_of_data },
1503+
{ .compatible = "samsung,exynos8890-pinctrl",
1504+
.data = &exynos8890_of_data },
15011505
{ .compatible = "samsung,exynos8895-pinctrl",
15021506
.data = &exynos8895_of_data },
15031507
{ .compatible = "samsung,exynos9810-pinctrl",

‎drivers/pinctrl/samsung/pinctrl-samsung.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -382,6 +382,7 @@ struct samsung_pmx_func {
382382

383383
/* list of all exported SoC specific data */
384384
extern const struct samsung_pinctrl_of_match_data artpec8_of_data;
385+
extern const struct samsung_pinctrl_of_match_data artpec9_of_data;
385386
extern const struct samsung_pinctrl_of_match_data exynos2200_of_data;
386387
extern const struct samsung_pinctrl_of_match_data exynos3250_of_data;
387388
extern const struct samsung_pinctrl_of_match_data exynos4210_of_data;
@@ -395,6 +396,7 @@ extern const struct samsung_pinctrl_of_match_data exynos7_of_data;
395396
extern const struct samsung_pinctrl_of_match_data exynos7870_of_data;
396397
extern const struct samsung_pinctrl_of_match_data exynos7885_of_data;
397398
extern const struct samsung_pinctrl_of_match_data exynos850_of_data;
399+
extern const struct samsung_pinctrl_of_match_data exynos8890_of_data;
398400
extern const struct samsung_pinctrl_of_match_data exynos8895_of_data;
399401
extern const struct samsung_pinctrl_of_match_data exynos9810_of_data;
400402
extern const struct samsung_pinctrl_of_match_data exynos990_of_data;

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