1111
1212#define SPINAND_MFR_FORESEE 0xCD
1313
14+ #define F35SQB002G_STATUS_ECC_MASK (7 << 4)
15+ #define F35SQB002G_STATUS_ECC_NO_BITFLIPS (0 << 4)
16+ #define F35SQB002G_STATUS_ECC_1_3_BITFLIPS (1 << 4)
17+ #define F35SQB002G_STATUS_ECC_UNCOR_ERROR (7 << 4)
18+
1419static SPINAND_OP_VARIANTS (read_cache_variants ,
1520 SPINAND_PAGE_READ_FROM_CACHE_1S_1S_4S_OP (0 , 1 , NULL, 0 , 0 ),
1621 SPINAND_PAGE_READ_FROM_CACHE_1S_1S_2S_OP (0 , 1 , NULL, 0 , 0 ),
@@ -70,6 +75,25 @@ static int f35sqa002g_ecc_get_status(struct spinand_device *spinand, u8 status)
7075 return - EBADMSG ;
7176}
7277
78+ static int f35sqb002g_ecc_get_status (struct spinand_device * spinand , u8 status )
79+ {
80+ switch (status & F35SQB002G_STATUS_ECC_MASK ) {
81+ case F35SQB002G_STATUS_ECC_NO_BITFLIPS :
82+ return 0 ;
83+
84+ case F35SQB002G_STATUS_ECC_1_3_BITFLIPS :
85+ return 3 ;
86+
87+ case F35SQB002G_STATUS_ECC_UNCOR_ERROR :
88+ return - EBADMSG ;
89+
90+ default : /* (2 << 4) through (6 << 4) are 4-8 corrected errors */
91+ return ((status & F35SQB002G_STATUS_ECC_MASK ) >> 4 ) + 2 ;
92+ }
93+
94+ return - EINVAL ;
95+ }
96+
7397static const struct spinand_info foresee_spinand_table [] = {
7498 SPINAND_INFO ("F35SQA002G ",
7599 SPINAND_ID (SPINAND_READID_METHOD_OPCODE_DUMMY , 0x72 , 0x72 ),
@@ -91,6 +115,16 @@ static const struct spinand_info foresee_spinand_table[] = {
91115 SPINAND_HAS_QE_BIT ,
92116 SPINAND_ECCINFO (& f35sqa002g_ooblayout ,
93117 f35sqa002g_ecc_get_status )),
118+ SPINAND_INFO ("F35SQB002G ",
119+ SPINAND_ID (SPINAND_READID_METHOD_OPCODE_DUMMY , 0x52 , 0x52 ),
120+ NAND_MEMORG (1 , 2048 , 128 , 64 , 2048 , 40 , 1 , 1 , 1 ),
121+ NAND_ECCREQ (8 , 512 ),
122+ SPINAND_INFO_OP_VARIANTS (& read_cache_variants ,
123+ & write_cache_variants ,
124+ & update_cache_variants ),
125+ SPINAND_HAS_QE_BIT ,
126+ SPINAND_ECCINFO (& f35sqa002g_ooblayout ,
127+ f35sqb002g_ecc_get_status )),
94128};
95129
96130static const struct spinand_manufacturer_ops foresee_spinand_manuf_ops = {
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