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Phil Edworthygeertu
Phil Edworthy
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geertu
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clk: renesas: Add RZ/V2M support using the rzg2l driver
The Renesas RZ/V2M SoC is very similar to RZ/G2L, though it doesn't have any CLK_MON registers. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220503115557.53370-11-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
1 parent 8090bea commit 1dd65bb

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‎drivers/clk/renesas/Kconfig‎

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@@ -37,6 +37,7 @@ config CLK_RENESAS
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select CLK_R9A07G043 if ARCH_R9A07G043
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select CLK_R9A07G044 if ARCH_R9A07G044
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select CLK_R9A07G054 if ARCH_R9A07G054
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select CLK_R9A09G011 if ARCH_R9A09G011
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select CLK_SH73A0 if ARCH_SH73A0
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if CLK_RENESAS
@@ -178,6 +179,10 @@ config CLK_R9A07G054
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bool "RZ/V2L clock support" if COMPILE_TEST
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select CLK_RZG2L
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config CLK_R9A09G011
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bool "RZ/V2M clock support" if COMPILE_TEST
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select CLK_RZG2L
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config CLK_SH73A0
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bool "SH-Mobile AG5 clock support" if COMPILE_TEST
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select CLK_RENESAS_CPG_MSTP

‎drivers/clk/renesas/Makefile‎

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@@ -34,6 +34,7 @@ obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o
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obj-$(CONFIG_CLK_R9A07G043) += r9a07g043-cpg.o
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obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o
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obj-$(CONFIG_CLK_R9A07G054) += r9a07g044-cpg.o
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obj-$(CONFIG_CLK_R9A09G011) += r9a09g011-cpg.o
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obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o
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# Family

‎drivers/clk/renesas/r9a09g011-cpg.c‎

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// SPDX-License-Identifier: GPL-2.0
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/*
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* RZ/V2M Clock Pulse Generator / Module Standby and Software Reset
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*
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* Copyright (C) 2022 Renesas Electronics Corp.
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*
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* Based on r9a07g044-cpg.c
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*/
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#include <linux/clk-provider.h>
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#include <linux/device.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <dt-bindings/clock/r9a09g011-cpg.h>
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#include "rzg2l-cpg.h"
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#define RZV2M_SAMPLL4_CLK1 0x104
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#define RZV2M_SAMPLL4_CLK2 0x108
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#define PLL4_CONF (RZV2M_SAMPLL4_CLK1 << 22 | RZV2M_SAMPLL4_CLK2 << 12)
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#define DIV_A DDIV_PACK(0x200, 0, 3)
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#define DIV_B DDIV_PACK(0x204, 0, 2)
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#define DIV_E DDIV_PACK(0x204, 8, 1)
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#define DIV_W DDIV_PACK(0x328, 0, 3)
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#define SEL_B SEL_PLL_PACK(0x214, 0, 1)
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#define SEL_E SEL_PLL_PACK(0x214, 2, 1)
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#define SEL_W0 SEL_PLL_PACK(0x32C, 0, 1)
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enum clk_ids {
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/* Core Clock Outputs exported to DT */
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LAST_DT_CORE_CLK = 0,
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/* External Input Clocks */
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CLK_EXTAL,
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/* Internal Core Clocks */
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CLK_MAIN,
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CLK_MAIN_24,
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CLK_MAIN_2,
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CLK_PLL1,
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CLK_PLL2,
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CLK_PLL2_800,
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CLK_PLL2_400,
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CLK_PLL2_200,
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CLK_PLL2_100,
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CLK_PLL4,
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CLK_DIV_A,
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CLK_DIV_B,
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CLK_DIV_E,
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CLK_DIV_W,
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CLK_SEL_B,
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CLK_SEL_B_D2,
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CLK_SEL_E,
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CLK_SEL_W0,
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/* Module Clocks */
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MOD_CLK_BASE
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};
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/* Divider tables */
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static const struct clk_div_table dtable_diva[] = {
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{0, 1},
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{1, 2},
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{2, 3},
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{3, 4},
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{4, 6},
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{5, 12},
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{6, 24},
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{0, 0},
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};
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static const struct clk_div_table dtable_divb[] = {
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{0, 1},
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{1, 2},
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{2, 4},
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{3, 8},
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{0, 0},
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};
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static const struct clk_div_table dtable_divw[] = {
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{0, 6},
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{1, 7},
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{2, 8},
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{3, 9},
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{4, 10},
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{5, 11},
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{6, 12},
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{0, 0},
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};
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/* Mux clock tables */
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static const char * const sel_b[] = { ".main", ".divb" };
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static const char * const sel_e[] = { ".main", ".dive" };
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static const char * const sel_w[] = { ".main", ".divw" };
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static const struct cpg_core_clk r9a09g011_core_clks[] __initconst = {
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/* External Clock Inputs */
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DEF_INPUT("extal", CLK_EXTAL),
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/* Internal Core Clocks */
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DEF_FIXED(".main", CLK_MAIN, CLK_EXTAL, 1, 1),
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DEF_FIXED(".main_24", CLK_MAIN_24, CLK_MAIN, 1, 2),
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DEF_FIXED(".main_2", CLK_MAIN_2, CLK_MAIN, 1, 24),
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DEF_FIXED(".pll1", CLK_PLL1, CLK_MAIN_2, 498, 1),
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DEF_FIXED(".pll2", CLK_PLL2, CLK_MAIN_2, 800, 1),
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DEF_FIXED(".pll2_800", CLK_PLL2_800, CLK_PLL2, 1, 2),
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DEF_FIXED(".pll2_400", CLK_PLL2_400, CLK_PLL2_800, 1, 2),
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DEF_FIXED(".pll2_200", CLK_PLL2_200, CLK_PLL2_800, 1, 4),
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DEF_FIXED(".pll2_100", CLK_PLL2_100, CLK_PLL2_800, 1, 8),
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DEF_SAMPLL(".pll4", CLK_PLL4, CLK_MAIN_2, PLL4_CONF),
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DEF_DIV_RO(".diva", CLK_DIV_A, CLK_PLL1, DIV_A, dtable_diva),
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DEF_DIV_RO(".divb", CLK_DIV_B, CLK_PLL2_400, DIV_B, dtable_divb),
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DEF_DIV_RO(".dive", CLK_DIV_E, CLK_PLL2_100, DIV_E, NULL),
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DEF_DIV_RO(".divw", CLK_DIV_W, CLK_PLL4, DIV_W, dtable_divw),
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DEF_MUX_RO(".selb", CLK_SEL_B, SEL_B, sel_b),
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DEF_MUX_RO(".sele", CLK_SEL_E, SEL_E, sel_e),
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DEF_MUX(".selw0", CLK_SEL_W0, SEL_W0, sel_w),
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DEF_FIXED(".selb_d2", CLK_SEL_B_D2, CLK_SEL_B, 1, 2),
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};
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static const struct rzg2l_mod_clk r9a09g011_mod_clks[] __initconst = {
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DEF_MOD("gic", R9A09G011_GIC_CLK, CLK_SEL_B_D2, 0x400, 5),
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DEF_MOD("syc_cnt_clk", R9A09G011_SYC_CNT_CLK, CLK_MAIN_24, 0x41c, 12),
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DEF_MOD("urt_pclk", R9A09G011_URT_PCLK, CLK_SEL_E, 0x438, 4),
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DEF_MOD("urt0_clk", R9A09G011_URT0_CLK, CLK_SEL_W0, 0x438, 5),
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DEF_MOD("ca53", R9A09G011_CA53_CLK, CLK_DIV_A, 0x448, 0),
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};
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static const struct rzg2l_reset r9a09g011_resets[] = {
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DEF_RST_MON(R9A09G011_SYC_RST_N, 0x610, 9, 13),
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};
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static const unsigned int r9a09g011_crit_mod_clks[] __initconst = {
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MOD_CLK_BASE + R9A09G011_CA53_CLK,
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MOD_CLK_BASE + R9A09G011_GIC_CLK,
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MOD_CLK_BASE + R9A09G011_SYC_CNT_CLK,
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MOD_CLK_BASE + R9A09G011_URT_PCLK,
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};
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const struct rzg2l_cpg_info r9a09g011_cpg_info = {
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/* Core Clocks */
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.core_clks = r9a09g011_core_clks,
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.num_core_clks = ARRAY_SIZE(r9a09g011_core_clks),
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.last_dt_core_clk = LAST_DT_CORE_CLK,
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.num_total_core_clks = MOD_CLK_BASE,
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/* Critical Module Clocks */
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.crit_mod_clks = r9a09g011_crit_mod_clks,
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.num_crit_mod_clks = ARRAY_SIZE(r9a09g011_crit_mod_clks),
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/* Module Clocks */
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.mod_clks = r9a09g011_mod_clks,
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.num_mod_clks = ARRAY_SIZE(r9a09g011_mod_clks),
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.num_hw_mod_clks = R9A09G011_CA53_CLK + 1,
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/* Resets */
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.resets = r9a09g011_resets,
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.num_resets = ARRAY_SIZE(r9a09g011_resets),
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.has_clk_mon_regs = false,
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};

‎drivers/clk/renesas/rzg2l-cpg.c‎

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@@ -1406,6 +1406,12 @@ static const struct of_device_id rzg2l_cpg_match[] = {
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.compatible = "renesas,r9a07g054-cpg",
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.data = &r9a07g054_cpg_info,
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},
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#endif
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#ifdef CONFIG_CLK_R9A09G011
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{
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.compatible = "renesas,r9a09g011-cpg",
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.data = &r9a09g011_cpg_info,
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},
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#endif
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{ /* sentinel */ }
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};

‎drivers/clk/renesas/rzg2l-cpg.h‎

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@@ -270,5 +270,6 @@ struct rzg2l_cpg_info {
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extern const struct rzg2l_cpg_info r9a07g043_cpg_info;
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extern const struct rzg2l_cpg_info r9a07g044_cpg_info;
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extern const struct rzg2l_cpg_info r9a07g054_cpg_info;
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extern const struct rzg2l_cpg_info r9a09g011_cpg_info;
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#endif

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