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zhaotianrui-loongsonchenhuacai
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LoongArch: KVM: Implement vcpu load and vcpu put operations
Implement LoongArch vcpu load and vcpu put operations, including load csr value into hardware and save csr value into vcpu structure. Reviewed-by: Bibo Mao <maobibo@loongson.cn> Tested-by: Huacai Chen <chenhuacai@loongson.cn> Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
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‎arch/loongarch/kvm/vcpu.c‎

Lines changed: 203 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -569,6 +569,209 @@ void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
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}
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}
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static int _kvm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
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{
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bool migrated;
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struct kvm_context *context;
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struct loongarch_csrs *csr = vcpu->arch.csr;
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/*
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* Have we migrated to a different CPU?
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* If so, any old guest TLB state may be stale.
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*/
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migrated = (vcpu->arch.last_sched_cpu != cpu);
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/*
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* Was this the last vCPU to run on this CPU?
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* If not, any old guest state from this vCPU will have been clobbered.
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*/
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context = per_cpu_ptr(vcpu->kvm->arch.vmcs, cpu);
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if (migrated || (context->last_vcpu != vcpu))
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vcpu->arch.aux_inuse &= ~KVM_LARCH_HWCSR_USABLE;
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context->last_vcpu = vcpu;
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/* Restore timer state regardless */
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kvm_restore_timer(vcpu);
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/* Control guest page CCA attribute */
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change_csr_gcfg(CSR_GCFG_MATC_MASK, CSR_GCFG_MATC_ROOT);
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/* Don't bother restoring registers multiple times unless necessary */
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if (vcpu->arch.aux_inuse & KVM_LARCH_HWCSR_USABLE)
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return 0;
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write_csr_gcntc((ulong)vcpu->kvm->arch.time_offset);
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/* Restore guest CSR registers */
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kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_CRMD);
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kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_PRMD);
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kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_EUEN);
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kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_MISC);
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kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_ECFG);
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kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_ERA);
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kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_BADV);
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kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_BADI);
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kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_EENTRY);
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kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_TLBIDX);
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kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_TLBEHI);
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kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_TLBELO0);
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kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_TLBELO1);
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kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_ASID);
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kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_PGDL);
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kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_PGDH);
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kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_PWCTL0);
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kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_PWCTL1);
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kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_STLBPGSIZE);
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kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_RVACFG);
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kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_CPUID);
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kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_KS0);
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kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_KS1);
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kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_KS2);
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kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_KS3);
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kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_KS4);
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kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_KS5);
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kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_KS6);
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kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_KS7);
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kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_TMID);
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kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_CNTC);
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kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_TLBRENTRY);
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kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_TLBRBADV);
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kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_TLBRERA);
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kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_TLBRSAVE);
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kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_TLBRELO0);
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kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_TLBRELO1);
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kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_TLBREHI);
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kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_TLBRPRMD);
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kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_DMWIN0);
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kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_DMWIN1);
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kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_DMWIN2);
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kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_DMWIN3);
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kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_LLBCTL);
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/* Restore Root.GINTC from unused Guest.GINTC register */
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write_csr_gintc(csr->csrs[LOONGARCH_CSR_GINTC]);
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/*
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* We should clear linked load bit to break interrupted atomics. This
656+
* prevents a SC on the next vCPU from succeeding by matching a LL on
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* the previous vCPU.
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*/
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if (vcpu->kvm->created_vcpus > 1)
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set_gcsr_llbctl(CSR_LLBCTL_WCLLB);
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vcpu->arch.aux_inuse |= KVM_LARCH_HWCSR_USABLE;
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return 0;
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}
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void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
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{
669+
unsigned long flags;
670+
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local_irq_save(flags);
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if (vcpu->arch.last_sched_cpu != cpu) {
673+
kvm_debug("[%d->%d]KVM vCPU[%d] switch\n",
674+
vcpu->arch.last_sched_cpu, cpu, vcpu->vcpu_id);
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/*
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* Migrate the timer interrupt to the current CPU so that it
677+
* always interrupts the guest and synchronously triggers a
678+
* guest timer interrupt.
679+
*/
680+
kvm_migrate_count(vcpu);
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}
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683+
/* Restore guest state to registers */
684+
_kvm_vcpu_load(vcpu, cpu);
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local_irq_restore(flags);
686+
}
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688+
static int _kvm_vcpu_put(struct kvm_vcpu *vcpu, int cpu)
689+
{
690+
struct loongarch_csrs *csr = vcpu->arch.csr;
691+
692+
kvm_lose_fpu(vcpu);
693+
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/*
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* Update CSR state from hardware if software CSR state is stale,
696+
* most CSR registers are kept unchanged during process context
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* switch except CSR registers like remaining timer tick value and
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* injected interrupt state.
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*/
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if (vcpu->arch.aux_inuse & KVM_LARCH_SWCSR_LATEST)
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goto out;
702+
703+
kvm_save_hw_gcsr(csr, LOONGARCH_CSR_CRMD);
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kvm_save_hw_gcsr(csr, LOONGARCH_CSR_PRMD);
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kvm_save_hw_gcsr(csr, LOONGARCH_CSR_EUEN);
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kvm_save_hw_gcsr(csr, LOONGARCH_CSR_MISC);
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kvm_save_hw_gcsr(csr, LOONGARCH_CSR_ECFG);
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kvm_save_hw_gcsr(csr, LOONGARCH_CSR_ERA);
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kvm_save_hw_gcsr(csr, LOONGARCH_CSR_BADV);
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kvm_save_hw_gcsr(csr, LOONGARCH_CSR_BADI);
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kvm_save_hw_gcsr(csr, LOONGARCH_CSR_EENTRY);
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kvm_save_hw_gcsr(csr, LOONGARCH_CSR_TLBIDX);
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kvm_save_hw_gcsr(csr, LOONGARCH_CSR_TLBEHI);
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kvm_save_hw_gcsr(csr, LOONGARCH_CSR_TLBELO0);
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kvm_save_hw_gcsr(csr, LOONGARCH_CSR_TLBELO1);
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kvm_save_hw_gcsr(csr, LOONGARCH_CSR_ASID);
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kvm_save_hw_gcsr(csr, LOONGARCH_CSR_PGDL);
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kvm_save_hw_gcsr(csr, LOONGARCH_CSR_PGDH);
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kvm_save_hw_gcsr(csr, LOONGARCH_CSR_PWCTL0);
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kvm_save_hw_gcsr(csr, LOONGARCH_CSR_PWCTL1);
721+
kvm_save_hw_gcsr(csr, LOONGARCH_CSR_STLBPGSIZE);
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kvm_save_hw_gcsr(csr, LOONGARCH_CSR_RVACFG);
723+
kvm_save_hw_gcsr(csr, LOONGARCH_CSR_CPUID);
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kvm_save_hw_gcsr(csr, LOONGARCH_CSR_PRCFG1);
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kvm_save_hw_gcsr(csr, LOONGARCH_CSR_PRCFG2);
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kvm_save_hw_gcsr(csr, LOONGARCH_CSR_PRCFG3);
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kvm_save_hw_gcsr(csr, LOONGARCH_CSR_KS0);
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kvm_save_hw_gcsr(csr, LOONGARCH_CSR_KS1);
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kvm_save_hw_gcsr(csr, LOONGARCH_CSR_KS2);
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kvm_save_hw_gcsr(csr, LOONGARCH_CSR_KS3);
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kvm_save_hw_gcsr(csr, LOONGARCH_CSR_KS4);
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kvm_save_hw_gcsr(csr, LOONGARCH_CSR_KS5);
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kvm_save_hw_gcsr(csr, LOONGARCH_CSR_KS6);
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kvm_save_hw_gcsr(csr, LOONGARCH_CSR_KS7);
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kvm_save_hw_gcsr(csr, LOONGARCH_CSR_TMID);
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kvm_save_hw_gcsr(csr, LOONGARCH_CSR_CNTC);
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kvm_save_hw_gcsr(csr, LOONGARCH_CSR_LLBCTL);
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kvm_save_hw_gcsr(csr, LOONGARCH_CSR_TLBRENTRY);
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kvm_save_hw_gcsr(csr, LOONGARCH_CSR_TLBRBADV);
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kvm_save_hw_gcsr(csr, LOONGARCH_CSR_TLBRERA);
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kvm_save_hw_gcsr(csr, LOONGARCH_CSR_TLBRSAVE);
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kvm_save_hw_gcsr(csr, LOONGARCH_CSR_TLBRELO0);
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kvm_save_hw_gcsr(csr, LOONGARCH_CSR_TLBRELO1);
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kvm_save_hw_gcsr(csr, LOONGARCH_CSR_TLBREHI);
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kvm_save_hw_gcsr(csr, LOONGARCH_CSR_TLBRPRMD);
746+
kvm_save_hw_gcsr(csr, LOONGARCH_CSR_DMWIN0);
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kvm_save_hw_gcsr(csr, LOONGARCH_CSR_DMWIN1);
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kvm_save_hw_gcsr(csr, LOONGARCH_CSR_DMWIN2);
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kvm_save_hw_gcsr(csr, LOONGARCH_CSR_DMWIN3);
750+
751+
vcpu->arch.aux_inuse |= KVM_LARCH_SWCSR_LATEST;
752+
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out:
754+
kvm_save_timer(vcpu);
755+
/* Save Root.GINTC into unused Guest.GINTC register */
756+
csr->csrs[LOONGARCH_CSR_GINTC] = read_csr_gintc();
757+
758+
return 0;
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}
760+
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void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
762+
{
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int cpu;
764+
unsigned long flags;
765+
766+
local_irq_save(flags);
767+
cpu = smp_processor_id();
768+
vcpu->arch.last_sched_cpu = cpu;
769+
770+
/* Save guest state in registers */
771+
_kvm_vcpu_put(vcpu, cpu);
772+
local_irq_restore(flags);
773+
}
774+
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int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu)
573776
{
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int r = -EINTR;

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