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Jack Xiaoalexdeucher
Jack Xiao
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alexdeucher
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drm/amdgpu/mes: add multiple mes ring instances support
Add multiple mes ring instances in mes structure to support multiple mes pipes. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit c7d4355)
1 parent 278e186 commit 2029b3d

9 files changed

Lines changed: 47 additions & 44 deletions

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‎drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -995,7 +995,7 @@ uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg, uint32_t xcc_
995995
if (amdgpu_device_skip_hw_access(adev))
996996
return 0;
997997

998-
if (adev->mes.ring.sched.ready)
998+
if (adev->mes.ring[0].sched.ready)
999999
return amdgpu_mes_rreg(adev, reg);
10001000

10011001
BUG_ON(!ring->funcs->emit_rreg);
@@ -1065,7 +1065,7 @@ void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, uint3
10651065
if (amdgpu_device_skip_hw_access(adev))
10661066
return;
10671067

1068-
if (adev->mes.ring.sched.ready) {
1068+
if (adev->mes.ring[0].sched.ready) {
10691069
amdgpu_mes_wreg(adev, reg, v);
10701070
return;
10711071
}

‎drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -589,7 +589,8 @@ int amdgpu_gmc_allocate_vm_inv_eng(struct amdgpu_device *adev)
589589
ring = adev->rings[i];
590590
vmhub = ring->vm_hub;
591591

592-
if (ring == &adev->mes.ring ||
592+
if (ring == &adev->mes.ring[0] ||
593+
ring == &adev->mes.ring[1] ||
593594
ring == &adev->umsch_mm.ring)
594595
continue;
595596

@@ -761,7 +762,7 @@ void amdgpu_gmc_fw_reg_write_reg_wait(struct amdgpu_device *adev,
761762
unsigned long flags;
762763
uint32_t seq;
763764

764-
if (adev->mes.ring.sched.ready) {
765+
if (adev->mes.ring[0].sched.ready) {
765766
amdgpu_mes_reg_write_reg_wait(adev, reg0, reg1,
766767
ref, mask);
767768
return;

‎drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -135,9 +135,11 @@ int amdgpu_mes_init(struct amdgpu_device *adev)
135135
idr_init(&adev->mes.queue_id_idr);
136136
ida_init(&adev->mes.doorbell_ida);
137137
spin_lock_init(&adev->mes.queue_id_lock);
138-
spin_lock_init(&adev->mes.ring_lock);
139138
mutex_init(&adev->mes.mutex_hidden);
140139

140+
for (i = 0; i < AMDGPU_MAX_MES_PIPES; i++)
141+
spin_lock_init(&adev->mes.ring_lock[i]);
142+
141143
adev->mes.total_max_queue = AMDGPU_FENCE_MES_QUEUE_ID_MASK;
142144
adev->mes.vmid_mask_mmhub = 0xffffff00;
143145
adev->mes.vmid_mask_gfxhub = 0xffffff00;

‎drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -82,8 +82,8 @@ struct amdgpu_mes {
8282
uint64_t default_process_quantum;
8383
uint64_t default_gang_quantum;
8484

85-
struct amdgpu_ring ring;
86-
spinlock_t ring_lock;
85+
struct amdgpu_ring ring[AMDGPU_MAX_MES_PIPES];
86+
spinlock_t ring_lock[AMDGPU_MAX_MES_PIPES];
8787

8888
const struct firmware *fw[AMDGPU_MAX_MES_PIPES];
8989

‎drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -858,7 +858,7 @@ void amdgpu_virt_post_reset(struct amdgpu_device *adev)
858858
adev->gfx.is_poweron = false;
859859
}
860860

861-
adev->mes.ring.sched.ready = false;
861+
adev->mes.ring[0].sched.ready = false;
862862
}
863863

864864
bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev, uint32_t ucode_id)

‎drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -231,7 +231,7 @@ static void gmc_v11_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
231231
/* This is necessary for SRIOV as well as for GFXOFF to function
232232
* properly under bare metal
233233
*/
234-
if ((adev->gfx.kiq[0].ring.sched.ready || adev->mes.ring.sched.ready) &&
234+
if ((adev->gfx.kiq[0].ring.sched.ready || adev->mes.ring[0].sched.ready) &&
235235
(amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) {
236236
amdgpu_gmc_fw_reg_write_reg_wait(adev, req, ack, inv_req,
237237
1 << vmid, GET_INST(GC, 0));

‎drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -299,7 +299,7 @@ static void gmc_v12_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
299299
/* This is necessary for SRIOV as well as for GFXOFF to function
300300
* properly under bare metal
301301
*/
302-
if ((adev->gfx.kiq[0].ring.sched.ready || adev->mes.ring.sched.ready) &&
302+
if ((adev->gfx.kiq[0].ring.sched.ready || adev->mes.ring[0].sched.ready) &&
303303
(amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) {
304304
struct amdgpu_vmhub *hub = &adev->vmhub[vmhub];
305305
const unsigned eng = 17;

‎drivers/gpu/drm/amd/amdgpu/mes_v11_0.c‎

Lines changed: 17 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -162,7 +162,7 @@ static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes,
162162
union MESAPI__QUERY_MES_STATUS mes_status_pkt;
163163
signed long timeout = 3000000; /* 3000 ms */
164164
struct amdgpu_device *adev = mes->adev;
165-
struct amdgpu_ring *ring = &mes->ring;
165+
struct amdgpu_ring *ring = &mes->ring[0];
166166
struct MES_API_STATUS *api_status;
167167
union MESAPI__MISC *x_pkt = pkt;
168168
const char *op_str, *misc_op_str;
@@ -191,7 +191,7 @@ static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes,
191191
status_ptr = (u64 *)&adev->wb.wb[status_offset];
192192
*status_ptr = 0;
193193

194-
spin_lock_irqsave(&mes->ring_lock, flags);
194+
spin_lock_irqsave(&mes->ring_lock[0], flags);
195195
r = amdgpu_ring_alloc(ring, (size + sizeof(mes_status_pkt)) / 4);
196196
if (r)
197197
goto error_unlock_free;
@@ -221,7 +221,7 @@ static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes,
221221
sizeof(mes_status_pkt) / 4);
222222

223223
amdgpu_ring_commit(ring);
224-
spin_unlock_irqrestore(&mes->ring_lock, flags);
224+
spin_unlock_irqrestore(&mes->ring_lock[0], flags);
225225

226226
op_str = mes_v11_0_get_op_string(x_pkt);
227227
misc_op_str = mes_v11_0_get_misc_op_string(x_pkt);
@@ -263,7 +263,7 @@ static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes,
263263
amdgpu_ring_undo(ring);
264264

265265
error_unlock_free:
266-
spin_unlock_irqrestore(&mes->ring_lock, flags);
266+
spin_unlock_irqrestore(&mes->ring_lock[0], flags);
267267

268268
error_wb_free:
269269
amdgpu_device_wb_free(adev, status_offset);
@@ -1025,7 +1025,7 @@ static int mes_v11_0_kiq_enable_queue(struct amdgpu_device *adev)
10251025
return r;
10261026
}
10271027

1028-
kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring);
1028+
kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring[0]);
10291029

10301030
return amdgpu_ring_test_helper(kiq_ring);
10311031
}
@@ -1039,7 +1039,7 @@ static int mes_v11_0_queue_init(struct amdgpu_device *adev,
10391039
if (pipe == AMDGPU_MES_KIQ_PIPE)
10401040
ring = &adev->gfx.kiq[0].ring;
10411041
else if (pipe == AMDGPU_MES_SCHED_PIPE)
1042-
ring = &adev->mes.ring;
1042+
ring = &adev->mes.ring[0];
10431043
else
10441044
BUG();
10451045

@@ -1081,7 +1081,7 @@ static int mes_v11_0_ring_init(struct amdgpu_device *adev)
10811081
{
10821082
struct amdgpu_ring *ring;
10831083

1084-
ring = &adev->mes.ring;
1084+
ring = &adev->mes.ring[0];
10851085

10861086
ring->funcs = &mes_v11_0_ring_funcs;
10871087

@@ -1134,7 +1134,7 @@ static int mes_v11_0_mqd_sw_init(struct amdgpu_device *adev,
11341134
if (pipe == AMDGPU_MES_KIQ_PIPE)
11351135
ring = &adev->gfx.kiq[0].ring;
11361136
else if (pipe == AMDGPU_MES_SCHED_PIPE)
1137-
ring = &adev->mes.ring;
1137+
ring = &adev->mes.ring[0];
11381138
else
11391139
BUG();
11401140

@@ -1226,12 +1226,12 @@ static int mes_v11_0_sw_fini(void *handle)
12261226
&adev->gfx.kiq[0].ring.mqd_gpu_addr,
12271227
&adev->gfx.kiq[0].ring.mqd_ptr);
12281228

1229-
amdgpu_bo_free_kernel(&adev->mes.ring.mqd_obj,
1230-
&adev->mes.ring.mqd_gpu_addr,
1231-
&adev->mes.ring.mqd_ptr);
1229+
amdgpu_bo_free_kernel(&adev->mes.ring[0].mqd_obj,
1230+
&adev->mes.ring[0].mqd_gpu_addr,
1231+
&adev->mes.ring[0].mqd_ptr);
12321232

12331233
amdgpu_ring_fini(&adev->gfx.kiq[0].ring);
1234-
amdgpu_ring_fini(&adev->mes.ring);
1234+
amdgpu_ring_fini(&adev->mes.ring[0]);
12351235

12361236
if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
12371237
mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE);
@@ -1342,9 +1342,9 @@ static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev)
13421342

13431343
static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev)
13441344
{
1345-
if (adev->mes.ring.sched.ready) {
1346-
mes_v11_0_kiq_dequeue(&adev->mes.ring);
1347-
adev->mes.ring.sched.ready = false;
1345+
if (adev->mes.ring[0].sched.ready) {
1346+
mes_v11_0_kiq_dequeue(&adev->mes.ring[0]);
1347+
adev->mes.ring[0].sched.ready = false;
13481348
}
13491349

13501350
if (amdgpu_sriov_vf(adev)) {
@@ -1362,7 +1362,7 @@ static int mes_v11_0_hw_init(void *handle)
13621362
int r;
13631363
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
13641364

1365-
if (adev->mes.ring.sched.ready)
1365+
if (adev->mes.ring[0].sched.ready)
13661366
goto out;
13671367

13681368
if (!adev->enable_mes_kiq) {
@@ -1407,7 +1407,7 @@ static int mes_v11_0_hw_init(void *handle)
14071407
* with MES enabled.
14081408
*/
14091409
adev->gfx.kiq[0].ring.sched.ready = false;
1410-
adev->mes.ring.sched.ready = true;
1410+
adev->mes.ring[0].sched.ready = true;
14111411

14121412
return 0;
14131413

‎drivers/gpu/drm/amd/amdgpu/mes_v12_0.c‎

Lines changed: 17 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -148,7 +148,7 @@ static int mes_v12_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes,
148148
union MESAPI__QUERY_MES_STATUS mes_status_pkt;
149149
signed long timeout = 3000000; /* 3000 ms */
150150
struct amdgpu_device *adev = mes->adev;
151-
struct amdgpu_ring *ring = &mes->ring;
151+
struct amdgpu_ring *ring = &mes->ring[0];
152152
struct MES_API_STATUS *api_status;
153153
union MESAPI__MISC *x_pkt = pkt;
154154
const char *op_str, *misc_op_str;
@@ -177,7 +177,7 @@ static int mes_v12_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes,
177177
status_ptr = (u64 *)&adev->wb.wb[status_offset];
178178
*status_ptr = 0;
179179

180-
spin_lock_irqsave(&mes->ring_lock, flags);
180+
spin_lock_irqsave(&mes->ring_lock[0], flags);
181181
r = amdgpu_ring_alloc(ring, (size + sizeof(mes_status_pkt)) / 4);
182182
if (r)
183183
goto error_unlock_free;
@@ -207,7 +207,7 @@ static int mes_v12_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes,
207207
sizeof(mes_status_pkt) / 4);
208208

209209
amdgpu_ring_commit(ring);
210-
spin_unlock_irqrestore(&mes->ring_lock, flags);
210+
spin_unlock_irqrestore(&mes->ring_lock[0], flags);
211211

212212
op_str = mes_v12_0_get_op_string(x_pkt);
213213
misc_op_str = mes_v12_0_get_misc_op_string(x_pkt);
@@ -249,7 +249,7 @@ static int mes_v12_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes,
249249
amdgpu_ring_undo(ring);
250250

251251
error_unlock_free:
252-
spin_unlock_irqrestore(&mes->ring_lock, flags);
252+
spin_unlock_irqrestore(&mes->ring_lock[0], flags);
253253

254254
error_wb_free:
255255
amdgpu_device_wb_free(adev, status_offset);
@@ -1095,7 +1095,7 @@ static int mes_v12_0_kiq_enable_queue(struct amdgpu_device *adev)
10951095
return r;
10961096
}
10971097

1098-
kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring);
1098+
kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring[0]);
10991099

11001100
r = amdgpu_ring_test_ring(kiq_ring);
11011101
if (r) {
@@ -1114,7 +1114,7 @@ static int mes_v12_0_queue_init(struct amdgpu_device *adev,
11141114
if (pipe == AMDGPU_MES_KIQ_PIPE)
11151115
ring = &adev->gfx.kiq[0].ring;
11161116
else if (pipe == AMDGPU_MES_SCHED_PIPE)
1117-
ring = &adev->mes.ring;
1117+
ring = &adev->mes.ring[0];
11181118
else
11191119
BUG();
11201120

@@ -1160,7 +1160,7 @@ static int mes_v12_0_ring_init(struct amdgpu_device *adev)
11601160
{
11611161
struct amdgpu_ring *ring;
11621162

1163-
ring = &adev->mes.ring;
1163+
ring = &adev->mes.ring[0];
11641164

11651165
ring->funcs = &mes_v12_0_ring_funcs;
11661166

@@ -1213,7 +1213,7 @@ static int mes_v12_0_mqd_sw_init(struct amdgpu_device *adev,
12131213
if (pipe == AMDGPU_MES_KIQ_PIPE)
12141214
ring = &adev->gfx.kiq[0].ring;
12151215
else if (pipe == AMDGPU_MES_SCHED_PIPE)
1216-
ring = &adev->mes.ring;
1216+
ring = &adev->mes.ring[0];
12171217
else
12181218
BUG();
12191219

@@ -1302,12 +1302,12 @@ static int mes_v12_0_sw_fini(void *handle)
13021302
&adev->gfx.kiq[0].ring.mqd_gpu_addr,
13031303
&adev->gfx.kiq[0].ring.mqd_ptr);
13041304

1305-
amdgpu_bo_free_kernel(&adev->mes.ring.mqd_obj,
1306-
&adev->mes.ring.mqd_gpu_addr,
1307-
&adev->mes.ring.mqd_ptr);
1305+
amdgpu_bo_free_kernel(&adev->mes.ring[0].mqd_obj,
1306+
&adev->mes.ring[0].mqd_gpu_addr,
1307+
&adev->mes.ring[0].mqd_ptr);
13081308

13091309
amdgpu_ring_fini(&adev->gfx.kiq[0].ring);
1310-
amdgpu_ring_fini(&adev->mes.ring);
1310+
amdgpu_ring_fini(&adev->mes.ring[0]);
13111311

13121312
if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
13131313
mes_v12_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE);
@@ -1351,7 +1351,7 @@ static void mes_v12_0_kiq_dequeue_sched(struct amdgpu_device *adev)
13511351
soc21_grbm_select(adev, 0, 0, 0, 0);
13521352
mutex_unlock(&adev->srbm_mutex);
13531353

1354-
adev->mes.ring.sched.ready = false;
1354+
adev->mes.ring[0].sched.ready = false;
13551355
}
13561356

13571357
static void mes_v12_0_kiq_setting(struct amdgpu_ring *ring)
@@ -1415,9 +1415,9 @@ static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev)
14151415

14161416
static int mes_v12_0_kiq_hw_fini(struct amdgpu_device *adev)
14171417
{
1418-
if (adev->mes.ring.sched.ready) {
1418+
if (adev->mes.ring[0].sched.ready) {
14191419
mes_v12_0_kiq_dequeue_sched(adev);
1420-
adev->mes.ring.sched.ready = false;
1420+
adev->mes.ring[0].sched.ready = false;
14211421
}
14221422

14231423
mes_v12_0_enable(adev, false);
@@ -1430,7 +1430,7 @@ static int mes_v12_0_hw_init(void *handle)
14301430
int r;
14311431
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
14321432

1433-
if (adev->mes.ring.sched.ready)
1433+
if (adev->mes.ring[0].sched.ready)
14341434
goto out;
14351435

14361436
if (!adev->enable_mes_kiq || adev->enable_uni_mes) {
@@ -1482,7 +1482,7 @@ static int mes_v12_0_hw_init(void *handle)
14821482
* with MES enabled.
14831483
*/
14841484
adev->gfx.kiq[0].ring.sched.ready = false;
1485-
adev->mes.ring.sched.ready = true;
1485+
adev->mes.ring[0].sched.ready = true;
14861486

14871487
return 0;
14881488

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