Skip to content

Commit 207656f

Browse files
arndbarndb
committed
Merge branch 'nuvoton/ma35d1' into soc/newsoc
This patchset adds initial support for the Nuvoton ma35d1 SoC, including initial device tree, clock driver, reset driver, and serial driver. This patchset cover letter is based from the initial support for Nuvoton ma35d1 to keep tracking the version history. This patchset had been applied to Linux kernel 6.4.0-rc5 and tested on the Nuvoton ma35d1 SOM evaluation board. (ma35d1 information: https://www.nuvoton.com/products/microprocessors/arm-cortex-a35-mpus/) MA35D1 porting on linux-5.10.y can be found at: https://github.com/OpenNuvoton/MPU-Family Link: https://lore.kernel.org/linux-arm-kernel/20230605040749.67964-1-ychuang570808@gmail.com/ [arnd: merging everything aside from the serial port driver for now, as that is still waiting for an Ack] * nuvoton/ma35d1: reset: Add Nuvoton ma35d1 reset driver support clk: nuvoton: Add clock driver for ma35d1 clock controller arm64: dts: nuvoton: Add initial ma35d1 device tree dt-bindings: serial: Document ma35d1 uart controller dt-bindings: arm: Add initial bindings for Nuvoton platform dt-bindings: reset: nuvoton: Document ma35d1 reset control dt-bindings: clock: nuvoton: add binding for ma35d1 clock controller arm64: defconfig: Add support for Nuvoton MA35 family SoCs arm64: Kconfig.platforms: Add config for Nuvoton MA35 platform Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2 parents f1fcbaa + e4bb55d commit 207656f

25 files changed

Lines changed: 2614 additions & 3 deletions

‎Documentation/devicetree/bindings/arm/nuvoton/nuvoton,ma35d1.yaml‎

Lines changed: 30 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,30 @@
1+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/arm/nuvoton/nuvoton,ma35d1.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: Nuvoton MA35 series SoC based platforms
8+
9+
maintainers:
10+
- Jacky Huang <ychuang3@nuvoton.com>
11+
12+
description: |
13+
Boards with an ARMv8 based Nuvoton MA35 series SoC shall have
14+
the following properties.
15+
16+
properties:
17+
$nodename:
18+
const: '/'
19+
compatible:
20+
oneOf:
21+
22+
- description: MA35D1 based boards
23+
items:
24+
- enum:
25+
- nuvoton,ma35d1-iot
26+
- nuvoton,ma35d1-som
27+
- const: nuvoton,ma35d1
28+
29+
additionalProperties: true
30+
...

Documentation/devicetree/bindings/arm/npcm/npcm.yaml renamed to Documentation/devicetree/bindings/arm/nuvoton/nuvoton,npcm.yaml

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
22
%YAML 1.2
33
---
4-
$id: http://devicetree.org/schemas/arm/npcm/npcm.yaml#
4+
$id: http://devicetree.org/schemas/arm/nuvoton/nuvoton,npcm.yaml#
55
$schema: http://devicetree.org/meta-schemas/core.yaml#
66

77
title: NPCM Platforms

‎Documentation/devicetree/bindings/clock/nuvoton,ma35d1-clk.yaml‎

Lines changed: 63 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,63 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/clock/nuvoton,ma35d1-clk.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: Nuvoton MA35D1 Clock Controller Module
8+
9+
maintainers:
10+
- Chi-Fang Li <cfli0@nuvoton.com>
11+
- Jacky Huang <ychuang3@nuvoton.com>
12+
13+
description: |
14+
The MA35D1 clock controller generates clocks for the whole chip,
15+
including system clocks and all peripheral clocks.
16+
17+
See also:
18+
include/dt-bindings/clock/ma35d1-clk.h
19+
20+
properties:
21+
compatible:
22+
items:
23+
- const: nuvoton,ma35d1-clk
24+
25+
reg:
26+
maxItems: 1
27+
28+
"#clock-cells":
29+
const: 1
30+
31+
clocks:
32+
maxItems: 1
33+
34+
nuvoton,pll-mode:
35+
description:
36+
A list of PLL operation mode corresponding to CAPLL, DDRPLL, APLL,
37+
EPLL, and VPLL in sequential.
38+
maxItems: 5
39+
items:
40+
enum:
41+
- integer
42+
- fractional
43+
- spread-spectrum
44+
$ref: /schemas/types.yaml#/definitions/non-unique-string-array
45+
46+
required:
47+
- compatible
48+
- reg
49+
- "#clock-cells"
50+
- clocks
51+
52+
additionalProperties: false
53+
54+
examples:
55+
- |
56+
57+
clock-controller@40460200 {
58+
compatible = "nuvoton,ma35d1-clk";
59+
reg = <0x40460200 0x100>;
60+
#clock-cells = <1>;
61+
clocks = <&clk_hxt>;
62+
};
63+
...

‎Documentation/devicetree/bindings/reset/nuvoton,ma35d1-reset.yaml‎

Lines changed: 45 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,45 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/reset/nuvoton,ma35d1-reset.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: Nuvoton MA35D1 Reset Controller
8+
9+
maintainers:
10+
- Chi-Fang Li <cfli0@nuvoton.com>
11+
- Jacky Huang <ychuang3@nuvoton.com>
12+
13+
description:
14+
The system reset controller can be used to reset various peripheral
15+
controllers in MA35D1 SoC.
16+
17+
properties:
18+
compatible:
19+
items:
20+
- const: nuvoton,ma35d1-reset
21+
22+
reg:
23+
maxItems: 1
24+
25+
'#reset-cells':
26+
const: 1
27+
28+
required:
29+
- compatible
30+
- reg
31+
- '#reset-cells'
32+
33+
additionalProperties: false
34+
35+
examples:
36+
# system reset controller node:
37+
- |
38+
39+
system-management@40460000 {
40+
compatible = "nuvoton,ma35d1-reset";
41+
reg = <0x40460000 0x200>;
42+
#reset-cells = <1>;
43+
};
44+
...
45+

‎Documentation/devicetree/bindings/serial/nuvoton,ma35d1-serial.yaml‎

Lines changed: 48 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,48 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/serial/nuvoton,ma35d1-serial.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: Nuvoton MA35D1 Universal Asynchronous Receiver/Transmitter (UART)
8+
9+
maintainers:
10+
- Min-Jen Chen <mjchen@nuvoton.com>
11+
- Jacky Huang <ychuang3@nuvoton.com>
12+
13+
allOf:
14+
- $ref: serial.yaml
15+
16+
properties:
17+
compatible:
18+
const: nuvoton,ma35d1-uart
19+
20+
reg:
21+
maxItems: 1
22+
23+
interrupts:
24+
maxItems: 1
25+
26+
clocks:
27+
maxItems: 1
28+
29+
required:
30+
- compatible
31+
- reg
32+
- interrupts
33+
- clocks
34+
35+
unevaluatedProperties: false
36+
37+
examples:
38+
- |
39+
#include <dt-bindings/interrupt-controller/arm-gic.h>
40+
#include <dt-bindings/clock/nuvoton,ma35d1-clk.h>
41+
42+
serial@40700000 {
43+
compatible = "nuvoton,ma35d1-uart";
44+
reg = <0x40700000 0x100>;
45+
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
46+
clocks = <&clk UART0_GATE>;
47+
};
48+
...

Documentation/devicetree/bindings/arm/npcm/nuvoton,gcr.yaml renamed to Documentation/devicetree/bindings/soc/nuvoton/nuvoton,npcm-gcr.yaml

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
22
%YAML 1.2
33
---
4-
$id: http://devicetree.org/schemas/arm/npcm/nuvoton,gcr.yaml#
4+
$id: http://devicetree.org/schemas/soc/nuvoton/nuvoton,npcm-gcr.yaml#
55
$schema: http://devicetree.org/meta-schemas/core.yaml#
66

77
title: Global Control Registers block in Nuvoton SoCs

‎MAINTAINERS‎

Lines changed: 12 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2502,6 +2502,18 @@ F: drivers/rtc/rtc-ab8500.c
25022502
F: drivers/rtc/rtc-pl031.c
25032503
F: drivers/soc/ux500/
25042504

2505+
ARM/NUVOTON MA35 ARCHITECTURE
2506+
M: Jacky Huang <ychuang3@nuvoton.com>
2507+
M: Shan-Chun Hung <schung@nuvoton.com>
2508+
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
2509+
S: Supported
2510+
F: Documentation/devicetree/bindings/*/*/*ma35*
2511+
F: Documentation/devicetree/bindings/*/*ma35*
2512+
F: arch/arm64/boot/dts/nuvoton/*ma35*
2513+
F: drivers/*/*/*ma35*
2514+
F: drivers/*/*ma35*
2515+
K: ma35d1
2516+
25052517
ARM/NUVOTON NPCM ARCHITECTURE
25062518
M: Avi Fishman <avifishman70@gmail.com>
25072519
M: Tomer Maimon <tmaimon77@gmail.com>
@@ -2513,7 +2525,6 @@ L: openbmc@lists.ozlabs.org (moderated for non-subscribers)
25132525
S: Supported
25142526
F: Documentation/devicetree/bindings/*/*/*npcm*
25152527
F: Documentation/devicetree/bindings/*/*npcm*
2516-
F: Documentation/devicetree/bindings/arm/npcm/*
25172528
F: Documentation/devicetree/bindings/rtc/nuvoton,nct3018y.yaml
25182529
F: arch/arm/boot/dts/nuvoton-npcm*
25192530
F: arch/arm/mach-npcm/

‎arch/arm64/Kconfig.platforms‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -225,6 +225,14 @@ config ARCH_S32
225225

226226
endif
227227

228+
config ARCH_MA35
229+
bool "Nuvoton MA35 Architecture"
230+
select GPIOLIB
231+
select PINCTRL
232+
select RESET_CONTROLLER
233+
help
234+
This enables support for the ARMv8 based Nuvoton MA35 series SoCs.
235+
228236
config ARCH_NPCM
229237
bool "Nuvoton NPCM Architecture"
230238
select PINCTRL

‎arch/arm64/boot/dts/nuvoton/Makefile‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,2 +1,4 @@
11
# SPDX-License-Identifier: GPL-2.0
2+
dtb-$(CONFIG_ARCH_MA35) += ma35d1-iot-512m.dtb
3+
dtb-$(CONFIG_ARCH_MA35) += ma35d1-som-256m.dtb
24
dtb-$(CONFIG_ARCH_NPCM) += nuvoton-npcm845-evb.dtb

‎arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts‎

Lines changed: 56 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,56 @@
1+
// SPDX-License-Identifier: GPL-2.0
2+
/*
3+
* Copyright (C) 2023 Nuvoton Technology Corp.
4+
* Author: Shan-Chun Hung <schung@nuvoton.com>
5+
* Jacky huang <ychuang3@nuvoton.com>
6+
*/
7+
8+
/dts-v1/;
9+
#include "ma35d1.dtsi"
10+
11+
/ {
12+
model = "Nuvoton MA35D1-IoT";
13+
compatible = "nuvoton,ma35d1-iot", "nuvoton,ma35d1";
14+
15+
aliases {
16+
serial0 = &uart0;
17+
};
18+
19+
chosen {
20+
stdout-path = "serial0:115200n8";
21+
};
22+
23+
mem: memory@80000000 {
24+
device_type = "memory";
25+
reg = <0x00000000 0x80000000 0 0x20000000>; /* 512M DRAM */
26+
};
27+
28+
clk_hxt: clock-hxt {
29+
compatible = "fixed-clock";
30+
#clock-cells = <0>;
31+
clock-frequency = <24000000>;
32+
clock-output-names = "clk_hxt";
33+
};
34+
};
35+
36+
&uart0 {
37+
status = "okay";
38+
};
39+
40+
&clk {
41+
assigned-clocks = <&clk CAPLL>,
42+
<&clk DDRPLL>,
43+
<&clk APLL>,
44+
<&clk EPLL>,
45+
<&clk VPLL>;
46+
assigned-clock-rates = <800000000>,
47+
<266000000>,
48+
<180000000>,
49+
<500000000>,
50+
<102000000>;
51+
nuvoton,pll-mode = "integer",
52+
"fractional",
53+
"integer",
54+
"integer",
55+
"integer";
56+
};

0 commit comments

Comments
 (0)