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Merge tag 'renesas-dts-for-v6.10-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
Renesas DTS updates for v6.10 (take two) - Add external interrupt (IRQC) support for the RZ/Five SoC, - Add SPI (MSIOF), external interrupt (INTC-EX), and IOMMU support for the R-Car V4M SoC, - Miscellaneous fixes and improvements. * tag 'renesas-dts-for-v6.10-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: arm64: dts: renesas: r8a779h0: Link IOMMU consumers arm64: dts: renesas: r8a779h0: Add IPMMU nodes arm64: dts: renesas: r8a779h0: Add INTC-EX node arm64: dts: renesas: r8a779h0: Add MSIOF nodes arm64: dts: renesas: rzg3s-smarc-som: Enable eMMC by default riscv: dts: renesas: rzfive-smarc-som: Drop deleting interrupt properties from ETH0/1 nodes arm64: dts: renesas: r9a07g043: Move interrupt-parent property to common DTSI riscv: dts: renesas: r9a07g043f: Add IRQC node to RZ/Five SoC DTSI arm64: dts: renesas: s4sk: Fix ethernet0 alias Link: https://lore.kernel.org/r/cover.1714116737.git.geert+renesas@glider.be Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2 parents c7639b7 + f026b64 commit 2173e54

7 files changed

Lines changed: 306 additions & 24 deletions

File tree

‎arch/arm64/boot/dts/renesas/r8a779f4-s4sk.dts‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -14,9 +14,9 @@
1414
compatible = "renesas,s4sk", "renesas,r8a779f4", "renesas,r8a779f0";
1515

1616
aliases {
17-
serial0 = &hscif0;
18-
serial1 = &hscif1;
19-
eth0 = &rswitch;
17+
serial0 = &hscif0;
18+
serial1 = &hscif1;
19+
ethernet0 = &rswitch;
2020
};
2121

2222
chosen {

‎arch/arm64/boot/dts/renesas/r8a779h0.dtsi‎

Lines changed: 226 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -404,6 +404,22 @@
404404
#thermal-sensor-cells = <1>;
405405
};
406406

407+
intc_ex: interrupt-controller@e61c0000 {
408+
compatible = "renesas,intc-ex-r8a779h0", "renesas,irqc";
409+
#interrupt-cells = <2>;
410+
interrupt-controller;
411+
reg = <0 0xe61c0000 0 0x200>;
412+
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
413+
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
414+
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
415+
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
416+
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
417+
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
418+
clocks = <&cpg CPG_MOD 611>;
419+
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
420+
resets = <&cpg 611>;
421+
};
422+
407423
tmu0: timer@e61e0000 {
408424
compatible = "renesas,tmu-r8a779h0", "renesas,tmu";
409425
reg = <0 0xe61e0000 0 0x30>;
@@ -657,6 +673,7 @@
657673
phy-mode = "rgmii";
658674
rx-internal-delay-ps = <0>;
659675
tx-internal-delay-ps = <0>;
676+
iommus = <&ipmmu_hc 0>;
660677
#address-cells = <1>;
661678
#size-cells = <0>;
662679
status = "disabled";
@@ -826,6 +843,102 @@
826843
status = "disabled";
827844
};
828845

846+
msiof0: spi@e6e90000 {
847+
compatible = "renesas,msiof-r8a779h0",
848+
"renesas,rcar-gen4-msiof";
849+
reg = <0 0xe6e90000 0 0x0064>;
850+
interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
851+
clocks = <&cpg CPG_MOD 618>;
852+
dmas = <&dmac1 0x41>, <&dmac1 0x40>,
853+
<&dmac2 0x41>, <&dmac2 0x40>;
854+
dma-names = "tx", "rx", "tx", "rx";
855+
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
856+
resets = <&cpg 618>;
857+
#address-cells = <1>;
858+
#size-cells = <0>;
859+
status = "disabled";
860+
};
861+
862+
msiof1: spi@e6ea0000 {
863+
compatible = "renesas,msiof-r8a779h0",
864+
"renesas,rcar-gen4-msiof";
865+
reg = <0 0xe6ea0000 0 0x0064>;
866+
interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
867+
clocks = <&cpg CPG_MOD 619>;
868+
dmas = <&dmac1 0x43>, <&dmac1 0x42>,
869+
<&dmac2 0x43>, <&dmac2 0x42>;
870+
dma-names = "tx", "rx", "tx", "rx";
871+
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
872+
resets = <&cpg 619>;
873+
#address-cells = <1>;
874+
#size-cells = <0>;
875+
status = "disabled";
876+
};
877+
878+
msiof2: spi@e6c00000 {
879+
compatible = "renesas,msiof-r8a779h0",
880+
"renesas,rcar-gen4-msiof";
881+
reg = <0 0xe6c00000 0 0x0064>;
882+
interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
883+
clocks = <&cpg CPG_MOD 620>;
884+
dmas = <&dmac1 0x45>, <&dmac1 0x44>,
885+
<&dmac2 0x45>, <&dmac2 0x44>;
886+
dma-names = "tx", "rx", "tx", "rx";
887+
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
888+
resets = <&cpg 620>;
889+
#address-cells = <1>;
890+
#size-cells = <0>;
891+
status = "disabled";
892+
};
893+
894+
msiof3: spi@e6c10000 {
895+
compatible = "renesas,msiof-r8a779h0",
896+
"renesas,rcar-gen4-msiof";
897+
reg = <0 0xe6c10000 0 0x0064>;
898+
interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
899+
clocks = <&cpg CPG_MOD 621>;
900+
dmas = <&dmac1 0x47>, <&dmac1 0x46>,
901+
<&dmac2 0x47>, <&dmac2 0x46>;
902+
dma-names = "tx", "rx", "tx", "rx";
903+
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
904+
resets = <&cpg 621>;
905+
#address-cells = <1>;
906+
#size-cells = <0>;
907+
status = "disabled";
908+
};
909+
910+
msiof4: spi@e6c20000 {
911+
compatible = "renesas,msiof-r8a779h0",
912+
"renesas,rcar-gen4-msiof";
913+
reg = <0 0xe6c20000 0 0x0064>;
914+
interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
915+
clocks = <&cpg CPG_MOD 622>;
916+
dmas = <&dmac1 0x49>, <&dmac1 0x48>,
917+
<&dmac2 0x49>, <&dmac2 0x48>;
918+
dma-names = "tx", "rx", "tx", "rx";
919+
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
920+
resets = <&cpg 622>;
921+
#address-cells = <1>;
922+
#size-cells = <0>;
923+
status = "disabled";
924+
};
925+
926+
msiof5: spi@e6c28000 {
927+
compatible = "renesas,msiof-r8a779h0",
928+
"renesas,rcar-gen4-msiof";
929+
reg = <0 0xe6c28000 0 0x0064>;
930+
interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
931+
clocks = <&cpg CPG_MOD 623>;
932+
dmas = <&dmac1 0x4b>, <&dmac1 0x4a>,
933+
<&dmac2 0x4b>, <&dmac2 0x4a>;
934+
dma-names = "tx", "rx", "tx", "rx";
935+
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
936+
resets = <&cpg 623>;
937+
#address-cells = <1>;
938+
#size-cells = <0>;
939+
status = "disabled";
940+
};
941+
829942
dmac1: dma-controller@e7350000 {
830943
compatible = "renesas,dmac-r8a779h0",
831944
"renesas,rcar-gen4-dmac";
@@ -859,6 +972,14 @@
859972
resets = <&cpg 709>;
860973
#dma-cells = <1>;
861974
dma-channels = <16>;
975+
iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
976+
<&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
977+
<&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
978+
<&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
979+
<&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
980+
<&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
981+
<&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
982+
<&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
862983
};
863984

864985
dmac2: dma-controller@e7351000 {
@@ -884,6 +1005,10 @@
8841005
resets = <&cpg 710>;
8851006
#dma-cells = <1>;
8861007
dma-channels = <8>;
1008+
iommus = <&ipmmu_ds0 16>, <&ipmmu_ds0 17>,
1009+
<&ipmmu_ds0 18>, <&ipmmu_ds0 19>,
1010+
<&ipmmu_ds0 20>, <&ipmmu_ds0 21>,
1011+
<&ipmmu_ds0 22>, <&ipmmu_ds0 23>;
8871012
};
8881013

8891014
mmc0: mmc@ee140000 {
@@ -897,6 +1022,7 @@
8971022
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
8981023
resets = <&cpg 706>;
8991024
max-frequency = <200000000>;
1025+
iommus = <&ipmmu_ds0 32>;
9001026
status = "disabled";
9011027
};
9021028

@@ -916,6 +1042,106 @@
9161042
status = "disabled";
9171043
};
9181044

1045+
ipmmu_rt0: iommu@ee480000 {
1046+
compatible = "renesas,ipmmu-r8a779h0",
1047+
"renesas,rcar-gen4-ipmmu-vmsa";
1048+
reg = <0 0xee480000 0 0x20000>;
1049+
renesas,ipmmu-main = <&ipmmu_mm>;
1050+
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
1051+
#iommu-cells = <1>;
1052+
};
1053+
1054+
ipmmu_rt1: iommu@ee4c0000 {
1055+
compatible = "renesas,ipmmu-r8a779h0",
1056+
"renesas,rcar-gen4-ipmmu-vmsa";
1057+
reg = <0 0xee4c0000 0 0x20000>;
1058+
renesas,ipmmu-main = <&ipmmu_mm>;
1059+
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
1060+
#iommu-cells = <1>;
1061+
};
1062+
1063+
ipmmu_ds0: iommu@eed00000 {
1064+
compatible = "renesas,ipmmu-r8a779h0",
1065+
"renesas,rcar-gen4-ipmmu-vmsa";
1066+
reg = <0 0xeed00000 0 0x20000>;
1067+
renesas,ipmmu-main = <&ipmmu_mm>;
1068+
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
1069+
#iommu-cells = <1>;
1070+
};
1071+
1072+
ipmmu_hc: iommu@eed40000 {
1073+
compatible = "renesas,ipmmu-r8a779h0",
1074+
"renesas,rcar-gen4-ipmmu-vmsa";
1075+
reg = <0 0xeed40000 0 0x20000>;
1076+
renesas,ipmmu-main = <&ipmmu_mm>;
1077+
power-domains = <&sysc R8A779H0_PD_C4>;
1078+
#iommu-cells = <1>;
1079+
};
1080+
1081+
ipmmu_ir: iommu@eed80000 {
1082+
compatible = "renesas,ipmmu-r8a779h0",
1083+
"renesas,rcar-gen4-ipmmu-vmsa";
1084+
reg = <0 0xeed80000 0 0x20000>;
1085+
renesas,ipmmu-main = <&ipmmu_mm>;
1086+
power-domains = <&sysc R8A779H0_PD_C4>;
1087+
#iommu-cells = <1>;
1088+
};
1089+
1090+
ipmmu_vc: iommu@eedc0000 {
1091+
compatible = "renesas,ipmmu-r8a779h0",
1092+
"renesas,rcar-gen4-ipmmu-vmsa";
1093+
reg = <0 0xeedc0000 0 0x20000>;
1094+
renesas,ipmmu-main = <&ipmmu_mm>;
1095+
power-domains = <&sysc R8A779H0_PD_C4>;
1096+
#iommu-cells = <1>;
1097+
};
1098+
1099+
ipmmu_3dg: iommu@eee00000 {
1100+
compatible = "renesas,ipmmu-r8a779h0",
1101+
"renesas,rcar-gen4-ipmmu-vmsa";
1102+
reg = <0 0xeee00000 0 0x20000>;
1103+
renesas,ipmmu-main = <&ipmmu_mm>;
1104+
power-domains = <&sysc R8A779H0_PD_C4>;
1105+
#iommu-cells = <1>;
1106+
};
1107+
1108+
ipmmu_vi0: iommu@eee80000 {
1109+
compatible = "renesas,ipmmu-r8a779h0",
1110+
"renesas,rcar-gen4-ipmmu-vmsa";
1111+
reg = <0 0xeee80000 0 0x20000>;
1112+
renesas,ipmmu-main = <&ipmmu_mm>;
1113+
power-domains = <&sysc R8A779H0_PD_C4>;
1114+
#iommu-cells = <1>;
1115+
};
1116+
1117+
ipmmu_vi1: iommu@eeec0000 {
1118+
compatible = "renesas,ipmmu-r8a779h0",
1119+
"renesas,rcar-gen4-ipmmu-vmsa";
1120+
reg = <0 0xeeec0000 0 0x20000>;
1121+
renesas,ipmmu-main = <&ipmmu_mm>;
1122+
power-domains = <&sysc R8A779H0_PD_C4>;
1123+
#iommu-cells = <1>;
1124+
};
1125+
1126+
ipmmu_vip0: iommu@eef00000 {
1127+
compatible = "renesas,ipmmu-r8a779h0",
1128+
"renesas,rcar-gen4-ipmmu-vmsa";
1129+
reg = <0 0xeef00000 0 0x20000>;
1130+
renesas,ipmmu-main = <&ipmmu_mm>;
1131+
power-domains = <&sysc R8A779H0_PD_C4>;
1132+
#iommu-cells = <1>;
1133+
};
1134+
1135+
ipmmu_mm: iommu@eefc0000 {
1136+
compatible = "renesas,ipmmu-r8a779h0",
1137+
"renesas,rcar-gen4-ipmmu-vmsa";
1138+
reg = <0 0xeefc0000 0 0x20000>;
1139+
interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
1140+
<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
1141+
power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
1142+
#iommu-cells = <1>;
1143+
};
1144+
9191145
gic: interrupt-controller@f1000000 {
9201146
compatible = "arm,gic-v3";
9211147
#interrupt-cells = <3>;

‎arch/arm64/boot/dts/renesas/r9a07g043.dtsi‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -598,6 +598,7 @@
598598
gpio-ranges = <&pinctrl 0 0 152>;
599599
#interrupt-cells = <2>;
600600
interrupt-controller;
601+
interrupt-parent = <&irqc>;
601602
clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>;
602603
power-domains = <&cpg>;
603604
resets = <&cpg R9A07G043_GPIO_RSTN>,

‎arch/arm64/boot/dts/renesas/r9a07g043u.dtsi‎

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -54,10 +54,6 @@
5454
};
5555
};
5656

57-
&pinctrl {
58-
interrupt-parent = <&irqc>;
59-
};
60-
6157
&soc {
6258
interrupt-parent = <&gic>;
6359

‎arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -25,7 +25,7 @@
2525
* SW_OFF - SD2 is connected to SoC
2626
* SW_ON - SCIF1, SSI0, IRQ0, IRQ1 connected to SoC
2727
*/
28-
#define SW_CONFIG2 SW_ON
28+
#define SW_CONFIG2 SW_OFF
2929
#define SW_CONFIG3 SW_ON
3030

3131
/ {

‎arch/riscv/boot/dts/renesas/r9a07g043f.dtsi‎

Lines changed: 75 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -54,6 +54,81 @@
5454
dma-noncoherent;
5555
interrupt-parent = <&plic>;
5656

57+
irqc: interrupt-controller@110a0000 {
58+
compatible = "renesas,r9a07g043f-irqc";
59+
reg = <0 0x110a0000 0 0x20000>;
60+
#interrupt-cells = <2>;
61+
#address-cells = <0>;
62+
interrupt-controller;
63+
interrupts = <32 IRQ_TYPE_LEVEL_HIGH>,
64+
<33 IRQ_TYPE_LEVEL_HIGH>,
65+
<34 IRQ_TYPE_LEVEL_HIGH>,
66+
<35 IRQ_TYPE_LEVEL_HIGH>,
67+
<36 IRQ_TYPE_LEVEL_HIGH>,
68+
<37 IRQ_TYPE_LEVEL_HIGH>,
69+
<38 IRQ_TYPE_LEVEL_HIGH>,
70+
<39 IRQ_TYPE_LEVEL_HIGH>,
71+
<40 IRQ_TYPE_LEVEL_HIGH>,
72+
<476 IRQ_TYPE_LEVEL_HIGH>,
73+
<477 IRQ_TYPE_LEVEL_HIGH>,
74+
<478 IRQ_TYPE_LEVEL_HIGH>,
75+
<479 IRQ_TYPE_LEVEL_HIGH>,
76+
<480 IRQ_TYPE_LEVEL_HIGH>,
77+
<481 IRQ_TYPE_LEVEL_HIGH>,
78+
<482 IRQ_TYPE_LEVEL_HIGH>,
79+
<483 IRQ_TYPE_LEVEL_HIGH>,
80+
<484 IRQ_TYPE_LEVEL_HIGH>,
81+
<485 IRQ_TYPE_LEVEL_HIGH>,
82+
<486 IRQ_TYPE_LEVEL_HIGH>,
83+
<487 IRQ_TYPE_LEVEL_HIGH>,
84+
<488 IRQ_TYPE_LEVEL_HIGH>,
85+
<489 IRQ_TYPE_LEVEL_HIGH>,
86+
<490 IRQ_TYPE_LEVEL_HIGH>,
87+
<491 IRQ_TYPE_LEVEL_HIGH>,
88+
<492 IRQ_TYPE_LEVEL_HIGH>,
89+
<493 IRQ_TYPE_LEVEL_HIGH>,
90+
<494 IRQ_TYPE_LEVEL_HIGH>,
91+
<495 IRQ_TYPE_LEVEL_HIGH>,
92+
<496 IRQ_TYPE_LEVEL_HIGH>,
93+
<497 IRQ_TYPE_LEVEL_HIGH>,
94+
<498 IRQ_TYPE_LEVEL_HIGH>,
95+
<499 IRQ_TYPE_LEVEL_HIGH>,
96+
<500 IRQ_TYPE_LEVEL_HIGH>,
97+
<501 IRQ_TYPE_LEVEL_HIGH>,
98+
<502 IRQ_TYPE_LEVEL_HIGH>,
99+
<503 IRQ_TYPE_LEVEL_HIGH>,
100+
<504 IRQ_TYPE_LEVEL_HIGH>,
101+
<505 IRQ_TYPE_LEVEL_HIGH>,
102+
<506 IRQ_TYPE_LEVEL_HIGH>,
103+
<507 IRQ_TYPE_LEVEL_HIGH>,
104+
<57 IRQ_TYPE_LEVEL_HIGH>,
105+
<66 IRQ_TYPE_EDGE_RISING>,
106+
<67 IRQ_TYPE_EDGE_RISING>,
107+
<68 IRQ_TYPE_EDGE_RISING>,
108+
<69 IRQ_TYPE_EDGE_RISING>,
109+
<70 IRQ_TYPE_EDGE_RISING>,
110+
<71 IRQ_TYPE_EDGE_RISING>;
111+
interrupt-names = "nmi",
112+
"irq0", "irq1", "irq2", "irq3",
113+
"irq4", "irq5", "irq6", "irq7",
114+
"tint0", "tint1", "tint2", "tint3",
115+
"tint4", "tint5", "tint6", "tint7",
116+
"tint8", "tint9", "tint10", "tint11",
117+
"tint12", "tint13", "tint14", "tint15",
118+
"tint16", "tint17", "tint18", "tint19",
119+
"tint20", "tint21", "tint22", "tint23",
120+
"tint24", "tint25", "tint26", "tint27",
121+
"tint28", "tint29", "tint30", "tint31",
122+
"bus-err", "ec7tie1-0", "ec7tie2-0",
123+
"ec7tiovf-0", "ec7tie1-1", "ec7tie2-1",
124+
"ec7tiovf-1";
125+
clocks = <&cpg CPG_MOD R9A07G043_IAX45_CLK>,
126+
<&cpg CPG_MOD R9A07G043_IAX45_PCLK>;
127+
clock-names = "clk", "pclk";
128+
power-domains = <&cpg>;
129+
resets = <&cpg R9A07G043_IAX45_RESETN>;
130+
};
131+
57132
plic: interrupt-controller@12c00000 {
58133
compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
59134
#interrupt-cells = <2>;

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