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pinctrl: samsung: Add Exynos 990 SoC pinctrl configuration
Add SoC pinctrl configuration for the Exynos 990. The bank types used are the same as Exynos 850, so we can reuse its macros. Signed-off-by: Igor Belwon <igor.belwon@mentallysanemainliners.org> Link: https://lore.kernel.org/r/20241016154838.64515-4-igor.belwon@mentallysanemainliners.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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‎drivers/pinctrl/samsung/pinctrl-exynos-arm64.c‎

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Original file line numberDiff line numberDiff line change
@@ -627,6 +627,146 @@ const struct samsung_pinctrl_of_match_data exynos850_of_data __initconst = {
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.num_ctrl = ARRAY_SIZE(exynos850_pin_ctrl),
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};
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/* pin banks of exynos990 pin-controller 0 (ALIVE) */
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static struct samsung_pin_bank_data exynos990_pin_banks0[] = {
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/* Must start with EINTG banks, ordered by EINT group number. */
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EXYNOS850_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
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EXYNOS850_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),
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EXYNOS850_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),
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EXYNOS850_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c),
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EXYNOS850_PIN_BANK_EINTW(2, 0x080, "gpa4", 0x10),
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EXYNOS850_PIN_BANK_EINTN(7, 0x0A0, "gpq0"),
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};
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/* pin banks of exynos990 pin-controller 1 (CMGP) */
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static struct samsung_pin_bank_data exynos990_pin_banks1[] = {
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/* Must start with EINTG banks, ordered by EINT group number. */
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EXYNOS850_PIN_BANK_EINTN(1, 0x000, "gpm0"),
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EXYNOS850_PIN_BANK_EINTN(1, 0x020, "gpm1"),
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EXYNOS850_PIN_BANK_EINTN(1, 0x040, "gpm2"),
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EXYNOS850_PIN_BANK_EINTN(1, 0x060, "gpm3"),
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EXYNOS850_PIN_BANK_EINTW(1, 0x080, "gpm4", 0x00),
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EXYNOS850_PIN_BANK_EINTW(1, 0x0A0, "gpm5", 0x04),
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EXYNOS850_PIN_BANK_EINTW(1, 0x0C0, "gpm6", 0x08),
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EXYNOS850_PIN_BANK_EINTW(1, 0x0E0, "gpm7", 0x0c),
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EXYNOS850_PIN_BANK_EINTW(1, 0x100, "gpm8", 0x10),
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EXYNOS850_PIN_BANK_EINTW(1, 0x120, "gpm9", 0x14),
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EXYNOS850_PIN_BANK_EINTW(1, 0x140, "gpm10", 0x18),
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EXYNOS850_PIN_BANK_EINTW(1, 0x160, "gpm11", 0x1c),
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EXYNOS850_PIN_BANK_EINTW(1, 0x180, "gpm12", 0x20),
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EXYNOS850_PIN_BANK_EINTW(1, 0x1A0, "gpm13", 0x24),
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EXYNOS850_PIN_BANK_EINTW(1, 0x1C0, "gpm14", 0x28),
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EXYNOS850_PIN_BANK_EINTW(1, 0x1E0, "gpm15", 0x2c),
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EXYNOS850_PIN_BANK_EINTW(1, 0x200, "gpm16", 0x30),
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EXYNOS850_PIN_BANK_EINTW(1, 0x220, "gpm17", 0x34),
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EXYNOS850_PIN_BANK_EINTW(1, 0x240, "gpm18", 0x38),
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EXYNOS850_PIN_BANK_EINTW(1, 0x260, "gpm19", 0x3c),
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EXYNOS850_PIN_BANK_EINTW(1, 0x280, "gpm20", 0x40),
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EXYNOS850_PIN_BANK_EINTW(1, 0x2A0, "gpm21", 0x44),
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EXYNOS850_PIN_BANK_EINTW(1, 0x2C0, "gpm22", 0x48),
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EXYNOS850_PIN_BANK_EINTW(1, 0x2E0, "gpm23", 0x4c),
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EXYNOS850_PIN_BANK_EINTW(1, 0x300, "gpm24", 0x50),
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EXYNOS850_PIN_BANK_EINTW(1, 0x320, "gpm25", 0x54),
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EXYNOS850_PIN_BANK_EINTW(1, 0x340, "gpm26", 0x58),
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EXYNOS850_PIN_BANK_EINTW(1, 0x360, "gpm27", 0x5c),
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EXYNOS850_PIN_BANK_EINTW(1, 0x380, "gpm28", 0x60),
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EXYNOS850_PIN_BANK_EINTW(1, 0x3A0, "gpm29", 0x64),
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EXYNOS850_PIN_BANK_EINTW(1, 0x3C0, "gpm30", 0x68),
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EXYNOS850_PIN_BANK_EINTW(1, 0x3E0, "gpm31", 0x6c),
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EXYNOS850_PIN_BANK_EINTW(1, 0x400, "gpm32", 0x70),
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EXYNOS850_PIN_BANK_EINTW(1, 0x420, "gpm33", 0x74),
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};
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/* pin banks of exynos990 pin-controller 2 (HSI1) */
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static struct samsung_pin_bank_data exynos990_pin_banks2[] = {
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/* Must start with EINTG banks, ordered by EINT group number. */
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EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpf0", 0x00),
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EXYNOS850_PIN_BANK_EINTG(6, 0x020, "gpf1", 0x04),
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EXYNOS850_PIN_BANK_EINTG(3, 0x040, "gpf2", 0x08),
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};
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/* pin banks of exynos990 pin-controller 3 (HSI2) */
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static struct samsung_pin_bank_data exynos990_pin_banks3[] = {
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/* Must start with EINTG banks, ordered by EINT group number. */
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EXYNOS850_PIN_BANK_EINTG(2, 0x000, "gpf3", 0x00),
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};
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/* pin banks of exynos990 pin-controller 4 (PERIC0) */
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static struct samsung_pin_bank_data exynos990_pin_banks4[] = {
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/* Must start with EINTG banks, ordered by EINT group number. */
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EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gpp0", 0x00),
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EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpp1", 0x04),
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EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpp2", 0x08),
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EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpp3", 0x0C),
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EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpp4", 0x10),
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EXYNOS850_PIN_BANK_EINTG(2, 0x0A0, "gpg0", 0x14),
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};
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/* pin banks of exynos990 pin-controller 5 (PERIC1) */
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static struct samsung_pin_bank_data exynos990_pin_banks5[] = {
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/* Must start with EINTG banks, ordered by EINT group number. */
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EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gpp5", 0x00),
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EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpp6", 0x04),
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EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpp7", 0x08),
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EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpp8", 0x0C),
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EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpp9", 0x10),
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EXYNOS850_PIN_BANK_EINTG(6, 0x0A0, "gpc0", 0x14),
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EXYNOS850_PIN_BANK_EINTG(4, 0x0C0, "gpg1", 0x18),
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EXYNOS850_PIN_BANK_EINTG(8, 0x0E0, "gpb0", 0x1C),
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EXYNOS850_PIN_BANK_EINTG(8, 0x100, "gpb1", 0x20),
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EXYNOS850_PIN_BANK_EINTG(8, 0x120, "gpb2", 0x24),
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};
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/* pin banks of exynos990 pin-controller 6 (VTS) */
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static struct samsung_pin_bank_data exynos990_pin_banks6[] = {
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/* Must start with EINTG banks, ordered by EINT group number. */
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EXYNOS850_PIN_BANK_EINTG(7, 0x000, "gpv0", 0x00),
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};
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static const struct samsung_pin_ctrl exynos990_pin_ctrl[] __initconst = {
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{
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/* pin-controller instance 0 ALIVE data */
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.pin_banks = exynos990_pin_banks0,
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.nr_banks = ARRAY_SIZE(exynos990_pin_banks0),
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.eint_wkup_init = exynos_eint_wkup_init,
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}, {
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/* pin-controller instance 1 CMGP data */
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.pin_banks = exynos990_pin_banks1,
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.nr_banks = ARRAY_SIZE(exynos990_pin_banks1),
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.eint_wkup_init = exynos_eint_wkup_init,
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}, {
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/* pin-controller instance 2 HSI1 data */
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.pin_banks = exynos990_pin_banks2,
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.nr_banks = ARRAY_SIZE(exynos990_pin_banks2),
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.eint_gpio_init = exynos_eint_gpio_init,
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}, {
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/* pin-controller instance 3 HSI2 data */
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.pin_banks = exynos990_pin_banks3,
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.nr_banks = ARRAY_SIZE(exynos990_pin_banks3),
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.eint_gpio_init = exynos_eint_gpio_init,
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}, {
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/* pin-controller instance 4 PERIC0 data */
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.pin_banks = exynos990_pin_banks4,
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.nr_banks = ARRAY_SIZE(exynos990_pin_banks4),
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.eint_gpio_init = exynos_eint_gpio_init,
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}, {
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/* pin-controller instance 5 PERIC1 data */
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.pin_banks = exynos990_pin_banks5,
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.nr_banks = ARRAY_SIZE(exynos990_pin_banks5),
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.eint_gpio_init = exynos_eint_gpio_init,
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}, {
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/* pin-controller instance 6 VTS data */
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.pin_banks = exynos990_pin_banks6,
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.nr_banks = ARRAY_SIZE(exynos990_pin_banks6),
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},
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};
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const struct samsung_pinctrl_of_match_data exynos990_of_data __initconst = {
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.ctrl = exynos990_pin_ctrl,
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.num_ctrl = ARRAY_SIZE(exynos990_pin_ctrl),
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};
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/* pin banks of exynosautov9 pin-controller 0 (ALIVE) */
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static const struct samsung_pin_bank_data exynosautov9_pin_banks0[] __initconst = {
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EXYNOS850_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),

‎drivers/pinctrl/samsung/pinctrl-samsung.c‎

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@@ -1479,6 +1479,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = {
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.data = &exynos850_of_data },
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{ .compatible = "samsung,exynos8895-pinctrl",
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.data = &exynos8895_of_data },
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{ .compatible = "samsung,exynos990-pinctrl",
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.data = &exynos990_of_data },
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{ .compatible = "samsung,exynosautov9-pinctrl",
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.data = &exynosautov9_of_data },
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{ .compatible = "samsung,exynosautov920-pinctrl",

‎drivers/pinctrl/samsung/pinctrl-samsung.h‎

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@@ -385,6 +385,7 @@ extern const struct samsung_pinctrl_of_match_data exynos7_of_data;
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extern const struct samsung_pinctrl_of_match_data exynos7885_of_data;
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extern const struct samsung_pinctrl_of_match_data exynos850_of_data;
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extern const struct samsung_pinctrl_of_match_data exynos8895_of_data;
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extern const struct samsung_pinctrl_of_match_data exynos990_of_data;
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extern const struct samsung_pinctrl_of_match_data exynosautov9_of_data;
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extern const struct samsung_pinctrl_of_match_data exynosautov920_of_data;
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extern const struct samsung_pinctrl_of_match_data fsd_of_data;

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