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Merge tag 'qcom-clk-for-5.18' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom
Pull Qualcomm clk driver updates from Bjorn Andersson: This introduces support for A7 PLL on SDX65, GPU clock controller for SM6350, display clock controller for SM6125, SM6350 and QCS2290 and multimedia clock controller for MSM8226. The RPMCC drivers get support for SC8280XP and MSM8992, MSM8994 and MSM8998 gains some missing clocks. A new gcc DeviceTree binding is introduced, to allow platform-specific GCC bindings to inherit common properties. The SDM845 camera clock controller binding is converted to YAML. SDM845 camera clock controller, SDM660 GPU clock controller, IPQ8074 global clock controller, IPQ806x global clock controller, SC7180 camera and video clock controllers, MSM8996 globacl clock controller are converted to parent_data and/or parent_hws and cleanups related to this. Test clocks are removed from the SC7180, SDM845 camera clock controller drivers and SDM660 GPU clock controller driver. IPQ806x gains clocks and resets for CryptoEngine and additional frequencies for SDCC and NSS cores. Floor ops are introduced for RCG clocks and used for IPQ8074 SDCC clocks. SM8150 gains EMAC, PCIe and UFS GDSCs. The RCG2 logic for calculating D value is updated to support pixel clock frequencies on newer platforms. * tag 'qcom-clk-for-5.18' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (59 commits) clk: qcom: Add display clock controller driver for SM6125 dt-bindings: clock: add QCOM SM6125 display clock bindings clk: qcom: Fix sorting of SDX_GCC_65 in Makefile and Kconfig clk: qcom: gcc: Add emac GDSC support for SM8150 clk: qcom: gcc: sm8150: Fix some identation issues clk: qcom: gcc: Add UFS_CARD and UFS_PHY GDSCs for SM8150 clk: qcom: gcc: Add PCIe0 and PCIe1 GDSC for SM8150 clk: qcom: clk-rcg2: Update the frac table for pixel clock clk: qcom: clk-rcg2: Update logic to calculate D value for RCG clk: qcom: smd: Add missing MSM8998 RPM clocks clk: qcom: smd: Add missing RPM clocks for msm8992/4 dt-bindings: clock: qcom: rpmcc: Add RPM Modem SubSystem (MSS) clocks clk: qcom: gcc-ipq806x: add CryptoEngine resets dt-bindings: reset: add ipq8064 ce5 resets clk: qcom: gcc-ipq806x: add CryptoEngine clocks dt-bindings: clock: add ipq8064 ce5 clk define clk: qcom: gcc-ipq806x: add additional freq for sdc table clk: qcom: clk-rcg: add clk_rcg_floor_ops ops clk: qcom: gcc-ipq806x: add unusued flag for critical clock clk: qcom: gcc-ipq806x: add additional freq nss cores ...
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42 files changed

Lines changed: 5027 additions & 985 deletions

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‎Documentation/devicetree/bindings/clock/qcom,a7pll.yaml‎

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- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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description:
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The A7 PLL on the Qualcomm platforms like SDX55 is used to provide high
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The A7 PLL on the Qualcomm platforms like SDX55, SDX65 is used to provide high
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frequency clock to the CPU.
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properties:

‎Documentation/devicetree/bindings/clock/qcom,camcc.txt‎

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This file was deleted.

‎Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm6125.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Display Clock Controller Binding for SM6125
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maintainers:
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- Martin Botka <martin.botka@somainline.org>
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description: |
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Qualcomm display clock control module which supports the clocks and
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power domains on SM6125.
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See also:
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dt-bindings/clock/qcom,dispcc-sm6125.h
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properties:
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compatible:
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enum:
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- qcom,sm6125-dispcc
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clocks:
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items:
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- description: Board XO source
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- description: Byte clock from DSI PHY0
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- description: Pixel clock from DSI PHY0
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- description: Pixel clock from DSI PHY1
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- description: Link clock from DP PHY
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- description: VCO DIV clock from DP PHY
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- description: AHB config clock from GCC
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clock-names:
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items:
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- const: bi_tcxo
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- const: dsi0_phy_pll_out_byteclk
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- const: dsi0_phy_pll_out_dsiclk
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- const: dsi1_phy_pll_out_dsiclk
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- const: dp_phy_pll_link_clk
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- const: dp_phy_pll_vco_div_clk
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- const: cfg_ahb_clk
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'#clock-cells':
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const: 1
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'#power-domain-cells':
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const: 1
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reg:
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maxItems: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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- '#power-domain-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmcc.h>
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#include <dt-bindings/clock/qcom,gcc-sm6125.h>
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clock-controller@5f00000 {
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compatible = "qcom,sm6125-dispcc";
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reg = <0x5f00000 0x20000>;
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clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
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<&dsi0_phy 0>,
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<&dsi0_phy 1>,
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<&dsi1_phy 1>,
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<&dp_phy 0>,
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<&dp_phy 1>,
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<&gcc GCC_DISP_AHB_CLK>;
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clock-names = "bi_tcxo",
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"dsi0_phy_pll_out_byteclk",
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"dsi0_phy_pll_out_dsiclk",
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"dsi1_phy_pll_out_dsiclk",
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"dp_phy_pll_link_clk",
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"dp_phy_pll_vco_div_clk",
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"cfg_ahb_clk";
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#clock-cells = <1>;
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#power-domain-cells = <1>;
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};
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...

‎Documentation/devicetree/bindings/clock/qcom,dispcc-sm6350.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm6350.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Display Clock & Reset Controller Binding for SM6350
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maintainers:
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- Konrad Dybcio <konrad.dybcio@somainline.org>
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description: |
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Qualcomm display clock control module which supports the clocks, resets and
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power domains on SM6350.
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See also dt-bindings/clock/qcom,dispcc-sm6350.h.
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properties:
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compatible:
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const: qcom,sm6350-dispcc
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clocks:
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items:
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- description: Board XO source
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- description: GPLL0 source from GCC
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- description: Byte clock from DSI PHY
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- description: Pixel clock from DSI PHY
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- description: Link clock from DP PHY
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- description: VCO DIV clock from DP PHY
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clock-names:
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items:
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- const: bi_tcxo
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- const: gcc_disp_gpll0_clk
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- const: dsi0_phy_pll_out_byteclk
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- const: dsi0_phy_pll_out_dsiclk
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- const: dp_phy_pll_link_clk
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- const: dp_phy_pll_vco_div_clk
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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'#power-domain-cells':
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const: 1
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reg:
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maxItems: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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- '#reset-cells'
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- '#power-domain-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-sm6350.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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clock-controller@af00000 {
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compatible = "qcom,sm6350-dispcc";
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reg = <0x0af00000 0x20000>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_DISP_GPLL0_CLK>,
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<&dsi_phy 0>,
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<&dsi_phy 1>,
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<&dp_phy 0>,
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<&dp_phy 1>;
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clock-names = "bi_tcxo",
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"gcc_disp_gpll0_clk",
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"dsi0_phy_pll_out_byteclk",
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"dsi0_phy_pll_out_dsiclk",
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"dp_phy_pll_link_clk",
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"dp_phy_pll_vco_div_clk";
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...

‎Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml‎

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title: Qualcomm Global Clock & Reset Controller Binding for APQ8064
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allOf:
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- $ref: qcom,gcc.yaml#
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maintainers:
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- Stephen Boyd <sboyd@kernel.org>
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- Taniya Das <tdas@codeaurora.org>
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See also:
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- dt-bindings/clock/qcom,gcc-msm8960.h
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- dt-bindings/reset/qcom,gcc-msm8960.h
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- dt-bindings/clock/qcom,gcc-apq8084.h
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- dt-bindings/reset/qcom,gcc-apq8084.h
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properties:
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compatible:
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const: qcom,gcc-apq8064
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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'#power-domain-cells':
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const: 1
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reg:
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maxItems: 1
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const: qcom,gcc-apq8084
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nvmem-cells:
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minItems: 1
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'#thermal-sensor-cells':
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const: 1
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protected-clocks:
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description:
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Protected clock specifier list as per common clock binding.
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required:
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- compatible
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- reg
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- '#clock-cells'
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- '#reset-cells'
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- '#power-domain-cells'
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- nvmem-cells
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- nvmem-cell-names
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- '#thermal-sensor-cells'
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additionalProperties: false
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unevaluatedProperties: false
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examples:
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- |

‎Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml‎

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,gcc-ipq8064.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Global Clock & Reset Controller Binding for IPQ8064
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allOf:
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- $ref: qcom,gcc.yaml#
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maintainers:
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- Ansuel Smith <ansuelsmth@gmail.com>
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description: |
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Qualcomm global clock control module which supports the clocks, resets and
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power domains on IPQ8064.
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See also:
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- dt-bindings/clock/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
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- dt-bindings/reset/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
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properties:
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compatible:
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items:
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- const: qcom,gcc-ipq8064
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- const: syscon
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clocks:
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items:
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- description: PXO source
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- description: CXO source
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clock-names:
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items:
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- const: pxo
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- const: cxo
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thermal-sensor:
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type: object
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allOf:
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- $ref: /schemas/thermal/qcom-tsens.yaml#
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required:
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- compatible
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- clocks
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- clock-names
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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gcc: clock-controller@900000 {
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compatible = "qcom,gcc-ipq8064", "syscon";
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reg = <0x00900000 0x4000>;
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clocks = <&pxo_board>, <&cxo_board>;
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clock-names = "pxo", "cxo";
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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tsens: thermal-sensor {
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compatible = "qcom,ipq8064-tsens";
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nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>;
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nvmem-cell-names = "calib", "calib_backup";
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interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "uplow";
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#qcom,sensors = <11>;
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#thermal-sensor-cells = <1>;
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};
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};

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