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tmlindbebarino
tmlind
authored and
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committed
clk: ti: Stop using legacy clkctrl names for omap4 and 5
With the addition of clock-output-names, we can now unify the internal clock naming for omap4 and 5 to follow the other TI SoCs. We are still using legacy clkctrl names for omap4 and 5 based on the clock manager name which is wrong. Instead, we want to use the clkctrl clock based naming. We must now also drop the legacy TI_CLK_CLKCTRL_COMPAT quirk for the clkctrl clock. This change will allow further devicetree warning cleanup as already done for am3/4 and dra7. Cc: linux-clk@vger.kernel.org Cc: Stephen Boyd <sboyd@kernel.org> Cc: Tero Kristo <kristo@kernel.org> Signed-off-by: Tony Lindgren <tony@atomide.com> Link: https://lore.kernel.org/r/20220615064306.22254-1-tony@atomide.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
1 parent f2906aa commit 255584b

3 files changed

Lines changed: 185 additions & 189 deletions

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‎drivers/clk/ti/clk-44xx.c‎

Lines changed: 105 additions & 105 deletions
Original file line numberDiff line numberDiff line change
@@ -56,7 +56,7 @@ static const struct omap_clkctrl_bit_data omap4_aess_bit_data[] __initconst = {
5656
};
5757

5858
static const char * const omap4_func_dmic_abe_gfclk_parents[] __initconst = {
59-
"abe_cm:clk:0018:26",
59+
"abe-clkctrl:0018:26",
6060
"pad_clks_ck",
6161
"slimbus_clk",
6262
NULL,
@@ -76,7 +76,7 @@ static const struct omap_clkctrl_bit_data omap4_dmic_bit_data[] __initconst = {
7676
};
7777

7878
static const char * const omap4_func_mcasp_abe_gfclk_parents[] __initconst = {
79-
"abe_cm:clk:0020:26",
79+
"abe-clkctrl:0020:26",
8080
"pad_clks_ck",
8181
"slimbus_clk",
8282
NULL,
@@ -89,7 +89,7 @@ static const struct omap_clkctrl_bit_data omap4_mcasp_bit_data[] __initconst = {
8989
};
9090

9191
static const char * const omap4_func_mcbsp1_gfclk_parents[] __initconst = {
92-
"abe_cm:clk:0028:26",
92+
"abe-clkctrl:0028:26",
9393
"pad_clks_ck",
9494
"slimbus_clk",
9595
NULL,
@@ -102,7 +102,7 @@ static const struct omap_clkctrl_bit_data omap4_mcbsp1_bit_data[] __initconst =
102102
};
103103

104104
static const char * const omap4_func_mcbsp2_gfclk_parents[] __initconst = {
105-
"abe_cm:clk:0030:26",
105+
"abe-clkctrl:0030:26",
106106
"pad_clks_ck",
107107
"slimbus_clk",
108108
NULL,
@@ -115,7 +115,7 @@ static const struct omap_clkctrl_bit_data omap4_mcbsp2_bit_data[] __initconst =
115115
};
116116

117117
static const char * const omap4_func_mcbsp3_gfclk_parents[] __initconst = {
118-
"abe_cm:clk:0038:26",
118+
"abe-clkctrl:0038:26",
119119
"pad_clks_ck",
120120
"slimbus_clk",
121121
NULL,
@@ -183,18 +183,18 @@ static const struct omap_clkctrl_bit_data omap4_timer8_bit_data[] __initconst =
183183

184184
static const struct omap_clkctrl_reg_data omap4_abe_clkctrl_regs[] __initconst = {
185185
{ OMAP4_L4_ABE_CLKCTRL, NULL, 0, "ocp_abe_iclk" },
186-
{ OMAP4_AESS_CLKCTRL, omap4_aess_bit_data, CLKF_SW_SUP, "abe_cm:clk:0008:24" },
186+
{ OMAP4_AESS_CLKCTRL, omap4_aess_bit_data, CLKF_SW_SUP, "abe-clkctrl:0008:24" },
187187
{ OMAP4_MCPDM_CLKCTRL, NULL, CLKF_SW_SUP, "pad_clks_ck" },
188-
{ OMAP4_DMIC_CLKCTRL, omap4_dmic_bit_data, CLKF_SW_SUP, "abe_cm:clk:0018:24" },
189-
{ OMAP4_MCASP_CLKCTRL, omap4_mcasp_bit_data, CLKF_SW_SUP, "abe_cm:clk:0020:24" },
190-
{ OMAP4_MCBSP1_CLKCTRL, omap4_mcbsp1_bit_data, CLKF_SW_SUP, "abe_cm:clk:0028:24" },
191-
{ OMAP4_MCBSP2_CLKCTRL, omap4_mcbsp2_bit_data, CLKF_SW_SUP, "abe_cm:clk:0030:24" },
192-
{ OMAP4_MCBSP3_CLKCTRL, omap4_mcbsp3_bit_data, CLKF_SW_SUP, "abe_cm:clk:0038:24" },
193-
{ OMAP4_SLIMBUS1_CLKCTRL, omap4_slimbus1_bit_data, CLKF_SW_SUP, "abe_cm:clk:0040:8" },
194-
{ OMAP4_TIMER5_CLKCTRL, omap4_timer5_bit_data, CLKF_SW_SUP, "abe_cm:clk:0048:24" },
195-
{ OMAP4_TIMER6_CLKCTRL, omap4_timer6_bit_data, CLKF_SW_SUP, "abe_cm:clk:0050:24" },
196-
{ OMAP4_TIMER7_CLKCTRL, omap4_timer7_bit_data, CLKF_SW_SUP, "abe_cm:clk:0058:24" },
197-
{ OMAP4_TIMER8_CLKCTRL, omap4_timer8_bit_data, CLKF_SW_SUP, "abe_cm:clk:0060:24" },
188+
{ OMAP4_DMIC_CLKCTRL, omap4_dmic_bit_data, CLKF_SW_SUP, "abe-clkctrl:0018:24" },
189+
{ OMAP4_MCASP_CLKCTRL, omap4_mcasp_bit_data, CLKF_SW_SUP, "abe-clkctrl:0020:24" },
190+
{ OMAP4_MCBSP1_CLKCTRL, omap4_mcbsp1_bit_data, CLKF_SW_SUP, "abe-clkctrl:0028:24" },
191+
{ OMAP4_MCBSP2_CLKCTRL, omap4_mcbsp2_bit_data, CLKF_SW_SUP, "abe-clkctrl:0030:24" },
192+
{ OMAP4_MCBSP3_CLKCTRL, omap4_mcbsp3_bit_data, CLKF_SW_SUP, "abe-clkctrl:0038:24" },
193+
{ OMAP4_SLIMBUS1_CLKCTRL, omap4_slimbus1_bit_data, CLKF_SW_SUP, "abe-clkctrl:0040:8" },
194+
{ OMAP4_TIMER5_CLKCTRL, omap4_timer5_bit_data, CLKF_SW_SUP, "abe-clkctrl:0048:24" },
195+
{ OMAP4_TIMER6_CLKCTRL, omap4_timer6_bit_data, CLKF_SW_SUP, "abe-clkctrl:0050:24" },
196+
{ OMAP4_TIMER7_CLKCTRL, omap4_timer7_bit_data, CLKF_SW_SUP, "abe-clkctrl:0058:24" },
197+
{ OMAP4_TIMER8_CLKCTRL, omap4_timer8_bit_data, CLKF_SW_SUP, "abe-clkctrl:0060:24" },
198198
{ OMAP4_WD_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
199199
{ 0 },
200200
};
@@ -287,7 +287,7 @@ static const struct omap_clkctrl_bit_data omap4_fdif_bit_data[] __initconst = {
287287

288288
static const struct omap_clkctrl_reg_data omap4_iss_clkctrl_regs[] __initconst = {
289289
{ OMAP4_ISS_CLKCTRL, omap4_iss_bit_data, CLKF_SW_SUP, "ducati_clk_mux_ck" },
290-
{ OMAP4_FDIF_CLKCTRL, omap4_fdif_bit_data, CLKF_SW_SUP, "iss_cm:clk:0008:24" },
290+
{ OMAP4_FDIF_CLKCTRL, omap4_fdif_bit_data, CLKF_SW_SUP, "iss-clkctrl:0008:24" },
291291
{ 0 },
292292
};
293293

@@ -320,7 +320,7 @@ static const struct omap_clkctrl_bit_data omap4_dss_core_bit_data[] __initconst
320320
};
321321

322322
static const struct omap_clkctrl_reg_data omap4_l3_dss_clkctrl_regs[] __initconst = {
323-
{ OMAP4_DSS_CORE_CLKCTRL, omap4_dss_core_bit_data, CLKF_SW_SUP, "l3_dss_cm:clk:0000:8" },
323+
{ OMAP4_DSS_CORE_CLKCTRL, omap4_dss_core_bit_data, CLKF_SW_SUP, "l3-dss-clkctrl:0000:8" },
324324
{ 0 },
325325
};
326326

@@ -336,7 +336,7 @@ static const struct omap_clkctrl_bit_data omap4_gpu_bit_data[] __initconst = {
336336
};
337337

338338
static const struct omap_clkctrl_reg_data omap4_l3_gfx_clkctrl_regs[] __initconst = {
339-
{ OMAP4_GPU_CLKCTRL, omap4_gpu_bit_data, CLKF_SW_SUP, "l3_gfx_cm:clk:0000:24" },
339+
{ OMAP4_GPU_CLKCTRL, omap4_gpu_bit_data, CLKF_SW_SUP, "l3-gfx-clkctrl:0000:24" },
340340
{ 0 },
341341
};
342342

@@ -372,12 +372,12 @@ static const struct omap_clkctrl_bit_data omap4_hsi_bit_data[] __initconst = {
372372
};
373373

374374
static const char * const omap4_usb_host_hs_utmi_p1_clk_parents[] __initconst = {
375-
"l3_init_cm:clk:0038:24",
375+
"l3-init-clkctrl:0038:24",
376376
NULL,
377377
};
378378

379379
static const char * const omap4_usb_host_hs_utmi_p2_clk_parents[] __initconst = {
380-
"l3_init_cm:clk:0038:25",
380+
"l3-init-clkctrl:0038:25",
381381
NULL,
382382
};
383383

@@ -418,7 +418,7 @@ static const struct omap_clkctrl_bit_data omap4_usb_host_hs_bit_data[] __initcon
418418
};
419419

420420
static const char * const omap4_usb_otg_hs_xclk_parents[] __initconst = {
421-
"l3_init_cm:clk:0040:24",
421+
"l3-init-clkctrl:0040:24",
422422
NULL,
423423
};
424424

@@ -452,14 +452,14 @@ static const struct omap_clkctrl_bit_data omap4_ocp2scp_usb_phy_bit_data[] __ini
452452
};
453453

454454
static const struct omap_clkctrl_reg_data omap4_l3_init_clkctrl_regs[] __initconst = {
455-
{ OMAP4_MMC1_CLKCTRL, omap4_mmc1_bit_data, CLKF_SW_SUP, "l3_init_cm:clk:0008:24" },
456-
{ OMAP4_MMC2_CLKCTRL, omap4_mmc2_bit_data, CLKF_SW_SUP, "l3_init_cm:clk:0010:24" },
457-
{ OMAP4_HSI_CLKCTRL, omap4_hsi_bit_data, CLKF_HW_SUP, "l3_init_cm:clk:0018:24" },
455+
{ OMAP4_MMC1_CLKCTRL, omap4_mmc1_bit_data, CLKF_SW_SUP, "l3-init-clkctrl:0008:24" },
456+
{ OMAP4_MMC2_CLKCTRL, omap4_mmc2_bit_data, CLKF_SW_SUP, "l3-init-clkctrl:0010:24" },
457+
{ OMAP4_HSI_CLKCTRL, omap4_hsi_bit_data, CLKF_HW_SUP, "l3-init-clkctrl:0018:24" },
458458
{ OMAP4_USB_HOST_HS_CLKCTRL, omap4_usb_host_hs_bit_data, CLKF_SW_SUP, "init_60m_fclk" },
459459
{ OMAP4_USB_OTG_HS_CLKCTRL, omap4_usb_otg_hs_bit_data, CLKF_HW_SUP, "l3_div_ck" },
460460
{ OMAP4_USB_TLL_HS_CLKCTRL, omap4_usb_tll_hs_bit_data, CLKF_HW_SUP, "l4_div_ck" },
461461
{ OMAP4_USB_HOST_FS_CLKCTRL, NULL, CLKF_SW_SUP, "func_48mc_fclk" },
462-
{ OMAP4_OCP2SCP_USB_PHY_CLKCTRL, omap4_ocp2scp_usb_phy_bit_data, CLKF_HW_SUP, "l3_init_cm:clk:00c0:8" },
462+
{ OMAP4_OCP2SCP_USB_PHY_CLKCTRL, omap4_ocp2scp_usb_phy_bit_data, CLKF_HW_SUP, "l3-init-clkctrl:00c0:8" },
463463
{ 0 },
464464
};
465465

@@ -530,7 +530,7 @@ static const struct omap_clkctrl_bit_data omap4_gpio6_bit_data[] __initconst = {
530530
};
531531

532532
static const char * const omap4_per_mcbsp4_gfclk_parents[] __initconst = {
533-
"l4_per_cm:clk:00c0:26",
533+
"l4-per-clkctrl:00c0:26",
534534
"pad_clks_ck",
535535
NULL,
536536
};
@@ -570,12 +570,12 @@ static const struct omap_clkctrl_bit_data omap4_slimbus2_bit_data[] __initconst
570570
};
571571

572572
static const struct omap_clkctrl_reg_data omap4_l4_per_clkctrl_regs[] __initconst = {
573-
{ OMAP4_TIMER10_CLKCTRL, omap4_timer10_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0008:24" },
574-
{ OMAP4_TIMER11_CLKCTRL, omap4_timer11_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0010:24" },
575-
{ OMAP4_TIMER2_CLKCTRL, omap4_timer2_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0018:24" },
576-
{ OMAP4_TIMER3_CLKCTRL, omap4_timer3_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0020:24" },
577-
{ OMAP4_TIMER4_CLKCTRL, omap4_timer4_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0028:24" },
578-
{ OMAP4_TIMER9_CLKCTRL, omap4_timer9_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0030:24" },
573+
{ OMAP4_TIMER10_CLKCTRL, omap4_timer10_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0008:24" },
574+
{ OMAP4_TIMER11_CLKCTRL, omap4_timer11_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0010:24" },
575+
{ OMAP4_TIMER2_CLKCTRL, omap4_timer2_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0018:24" },
576+
{ OMAP4_TIMER3_CLKCTRL, omap4_timer3_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0020:24" },
577+
{ OMAP4_TIMER4_CLKCTRL, omap4_timer4_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0028:24" },
578+
{ OMAP4_TIMER9_CLKCTRL, omap4_timer9_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0030:24" },
579579
{ OMAP4_ELM_CLKCTRL, NULL, 0, "l4_div_ck" },
580580
{ OMAP4_GPIO2_CLKCTRL, omap4_gpio2_bit_data, CLKF_HW_SUP, "l4_div_ck" },
581581
{ OMAP4_GPIO3_CLKCTRL, omap4_gpio3_bit_data, CLKF_HW_SUP, "l4_div_ck" },
@@ -588,14 +588,14 @@ static const struct omap_clkctrl_reg_data omap4_l4_per_clkctrl_regs[] __initcons
588588
{ OMAP4_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
589589
{ OMAP4_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
590590
{ OMAP4_L4_PER_CLKCTRL, NULL, 0, "l4_div_ck" },
591-
{ OMAP4_MCBSP4_CLKCTRL, omap4_mcbsp4_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:00c0:24" },
591+
{ OMAP4_MCBSP4_CLKCTRL, omap4_mcbsp4_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:00c0:24" },
592592
{ OMAP4_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
593593
{ OMAP4_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
594594
{ OMAP4_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
595595
{ OMAP4_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
596596
{ OMAP4_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
597597
{ OMAP4_MMC4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
598-
{ OMAP4_SLIMBUS2_CLKCTRL, omap4_slimbus2_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0118:8" },
598+
{ OMAP4_SLIMBUS2_CLKCTRL, omap4_slimbus2_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0118:8" },
599599
{ OMAP4_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
600600
{ OMAP4_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
601601
{ OMAP4_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
@@ -630,7 +630,7 @@ static const struct omap_clkctrl_reg_data omap4_l4_wkup_clkctrl_regs[] __initcon
630630
{ OMAP4_L4_WKUP_CLKCTRL, NULL, 0, "l4_wkup_clk_mux_ck" },
631631
{ OMAP4_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
632632
{ OMAP4_GPIO1_CLKCTRL, omap4_gpio1_bit_data, CLKF_HW_SUP, "l4_wkup_clk_mux_ck" },
633-
{ OMAP4_TIMER1_CLKCTRL, omap4_timer1_bit_data, CLKF_SW_SUP, "l4_wkup_cm:clk:0020:24" },
633+
{ OMAP4_TIMER1_CLKCTRL, omap4_timer1_bit_data, CLKF_SW_SUP, "l4-wkup-clkctrl:0020:24" },
634634
{ OMAP4_COUNTER_32K_CLKCTRL, NULL, 0, "sys_32k_ck" },
635635
{ OMAP4_KBD_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
636636
{ 0 },
@@ -644,7 +644,7 @@ static const char * const omap4_pmd_stm_clock_mux_ck_parents[] __initconst = {
644644
};
645645

646646
static const char * const omap4_trace_clk_div_div_ck_parents[] __initconst = {
647-
"emu_sys_cm:clk:0000:22",
647+
"emu-sys-clkctrl:0000:22",
648648
NULL,
649649
};
650650

@@ -662,7 +662,7 @@ static const struct omap_clkctrl_div_data omap4_trace_clk_div_div_ck_data __init
662662
};
663663

664664
static const char * const omap4_stm_clk_div_ck_parents[] __initconst = {
665-
"emu_sys_cm:clk:0000:20",
665+
"emu-sys-clkctrl:0000:20",
666666
NULL,
667667
};
668668

@@ -716,73 +716,73 @@ static struct ti_dt_clk omap44xx_clks[] = {
716716
* hwmod support. Once hwmod is removed, these can be removed
717717
* also.
718718
*/
719-
DT_CLK(NULL, "aess_fclk", "abe_cm:0008:24"),
720-
DT_CLK(NULL, "cm2_dm10_mux", "l4_per_cm:0008:24"),
721-
DT_CLK(NULL, "cm2_dm11_mux", "l4_per_cm:0010:24"),
722-
DT_CLK(NULL, "cm2_dm2_mux", "l4_per_cm:0018:24"),
723-
DT_CLK(NULL, "cm2_dm3_mux", "l4_per_cm:0020:24"),
724-
DT_CLK(NULL, "cm2_dm4_mux", "l4_per_cm:0028:24"),
725-
DT_CLK(NULL, "cm2_dm9_mux", "l4_per_cm:0030:24"),
726-
DT_CLK(NULL, "dmic_sync_mux_ck", "abe_cm:0018:26"),
727-
DT_CLK(NULL, "dmt1_clk_mux", "l4_wkup_cm:0020:24"),
728-
DT_CLK(NULL, "dss_48mhz_clk", "l3_dss_cm:0000:9"),
729-
DT_CLK(NULL, "dss_dss_clk", "l3_dss_cm:0000:8"),
730-
DT_CLK(NULL, "dss_sys_clk", "l3_dss_cm:0000:10"),
731-
DT_CLK(NULL, "dss_tv_clk", "l3_dss_cm:0000:11"),
732-
DT_CLK(NULL, "fdif_fck", "iss_cm:0008:24"),
733-
DT_CLK(NULL, "func_dmic_abe_gfclk", "abe_cm:0018:24"),
734-
DT_CLK(NULL, "func_mcasp_abe_gfclk", "abe_cm:0020:24"),
735-
DT_CLK(NULL, "func_mcbsp1_gfclk", "abe_cm:0028:24"),
736-
DT_CLK(NULL, "func_mcbsp2_gfclk", "abe_cm:0030:24"),
737-
DT_CLK(NULL, "func_mcbsp3_gfclk", "abe_cm:0038:24"),
738-
DT_CLK(NULL, "gpio1_dbclk", "l4_wkup_cm:0018:8"),
739-
DT_CLK(NULL, "gpio2_dbclk", "l4_per_cm:0040:8"),
740-
DT_CLK(NULL, "gpio3_dbclk", "l4_per_cm:0048:8"),
741-
DT_CLK(NULL, "gpio4_dbclk", "l4_per_cm:0050:8"),
742-
DT_CLK(NULL, "gpio5_dbclk", "l4_per_cm:0058:8"),
743-
DT_CLK(NULL, "gpio6_dbclk", "l4_per_cm:0060:8"),
744-
DT_CLK(NULL, "hsi_fck", "l3_init_cm:0018:24"),
745-
DT_CLK(NULL, "hsmmc1_fclk", "l3_init_cm:0008:24"),
746-
DT_CLK(NULL, "hsmmc2_fclk", "l3_init_cm:0010:24"),
747-
DT_CLK(NULL, "iss_ctrlclk", "iss_cm:0000:8"),
748-
DT_CLK(NULL, "mcasp_sync_mux_ck", "abe_cm:0020:26"),
749-
DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe_cm:0028:26"),
750-
DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe_cm:0030:26"),
751-
DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe_cm:0038:26"),
752-
DT_CLK(NULL, "mcbsp4_sync_mux_ck", "l4_per_cm:00c0:26"),
753-
DT_CLK(NULL, "ocp2scp_usb_phy_phy_48m", "l3_init_cm:00c0:8"),
754-
DT_CLK(NULL, "otg_60m_gfclk", "l3_init_cm:0040:24"),
755-
DT_CLK(NULL, "per_mcbsp4_gfclk", "l4_per_cm:00c0:24"),
756-
DT_CLK(NULL, "pmd_stm_clock_mux_ck", "emu_sys_cm:0000:20"),
757-
DT_CLK(NULL, "pmd_trace_clk_mux_ck", "emu_sys_cm:0000:22"),
758-
DT_CLK(NULL, "sgx_clk_mux", "l3_gfx_cm:0000:24"),
759-
DT_CLK(NULL, "slimbus1_fclk_0", "abe_cm:0040:8"),
760-
DT_CLK(NULL, "slimbus1_fclk_1", "abe_cm:0040:9"),
761-
DT_CLK(NULL, "slimbus1_fclk_2", "abe_cm:0040:10"),
762-
DT_CLK(NULL, "slimbus1_slimbus_clk", "abe_cm:0040:11"),
763-
DT_CLK(NULL, "slimbus2_fclk_0", "l4_per_cm:0118:8"),
764-
DT_CLK(NULL, "slimbus2_fclk_1", "l4_per_cm:0118:9"),
765-
DT_CLK(NULL, "slimbus2_slimbus_clk", "l4_per_cm:0118:10"),
766-
DT_CLK(NULL, "stm_clk_div_ck", "emu_sys_cm:0000:27"),
767-
DT_CLK(NULL, "timer5_sync_mux", "abe_cm:0048:24"),
768-
DT_CLK(NULL, "timer6_sync_mux", "abe_cm:0050:24"),
769-
DT_CLK(NULL, "timer7_sync_mux", "abe_cm:0058:24"),
770-
DT_CLK(NULL, "timer8_sync_mux", "abe_cm:0060:24"),
771-
DT_CLK(NULL, "trace_clk_div_div_ck", "emu_sys_cm:0000:24"),
772-
DT_CLK(NULL, "usb_host_hs_func48mclk", "l3_init_cm:0038:15"),
773-
DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "l3_init_cm:0038:13"),
774-
DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "l3_init_cm:0038:14"),
775-
DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "l3_init_cm:0038:11"),
776-
DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "l3_init_cm:0038:12"),
777-
DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "l3_init_cm:0038:8"),
778-
DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "l3_init_cm:0038:9"),
779-
DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "l3_init_cm:0038:10"),
780-
DT_CLK(NULL, "usb_otg_hs_xclk", "l3_init_cm:0040:8"),
781-
DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "l3_init_cm:0048:8"),
782-
DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "l3_init_cm:0048:9"),
783-
DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "l3_init_cm:0048:10"),
784-
DT_CLK(NULL, "utmi_p1_gfclk", "l3_init_cm:0038:24"),
785-
DT_CLK(NULL, "utmi_p2_gfclk", "l3_init_cm:0038:25"),
719+
DT_CLK(NULL, "aess_fclk", "abe-clkctrl:0008:24"),
720+
DT_CLK(NULL, "cm2_dm10_mux", "l4-per-clkctrl:0008:24"),
721+
DT_CLK(NULL, "cm2_dm11_mux", "l4-per-clkctrl:0010:24"),
722+
DT_CLK(NULL, "cm2_dm2_mux", "l4-per-clkctrl:0018:24"),
723+
DT_CLK(NULL, "cm2_dm3_mux", "l4-per-clkctrl:0020:24"),
724+
DT_CLK(NULL, "cm2_dm4_mux", "l4-per-clkctrl:0028:24"),
725+
DT_CLK(NULL, "cm2_dm9_mux", "l4-per-clkctrl:0030:24"),
726+
DT_CLK(NULL, "dmic_sync_mux_ck", "abe-clkctrl:0018:26"),
727+
DT_CLK(NULL, "dmt1_clk_mux", "l4-wkup-clkctrl:0020:24"),
728+
DT_CLK(NULL, "dss_48mhz_clk", "l3-dss-clkctrl:0000:9"),
729+
DT_CLK(NULL, "dss_dss_clk", "l3-dss-clkctrl:0000:8"),
730+
DT_CLK(NULL, "dss_sys_clk", "l3-dss-clkctrl:0000:10"),
731+
DT_CLK(NULL, "dss_tv_clk", "l3-dss-clkctrl:0000:11"),
732+
DT_CLK(NULL, "fdif_fck", "iss-clkctrl:0008:24"),
733+
DT_CLK(NULL, "func_dmic_abe_gfclk", "abe-clkctrl:0018:24"),
734+
DT_CLK(NULL, "func_mcasp_abe_gfclk", "abe-clkctrl:0020:24"),
735+
DT_CLK(NULL, "func_mcbsp1_gfclk", "abe-clkctrl:0028:24"),
736+
DT_CLK(NULL, "func_mcbsp2_gfclk", "abe-clkctrl:0030:24"),
737+
DT_CLK(NULL, "func_mcbsp3_gfclk", "abe-clkctrl:0038:24"),
738+
DT_CLK(NULL, "gpio1_dbclk", "l4-wkup-clkctrl:0018:8"),
739+
DT_CLK(NULL, "gpio2_dbclk", "l4-per-clkctrl:0040:8"),
740+
DT_CLK(NULL, "gpio3_dbclk", "l4-per-clkctrl:0048:8"),
741+
DT_CLK(NULL, "gpio4_dbclk", "l4-per-clkctrl:0050:8"),
742+
DT_CLK(NULL, "gpio5_dbclk", "l4-per-clkctrl:0058:8"),
743+
DT_CLK(NULL, "gpio6_dbclk", "l4-per-clkctrl:0060:8"),
744+
DT_CLK(NULL, "hsi_fck", "l3-init-clkctrl:0018:24"),
745+
DT_CLK(NULL, "hsmmc1_fclk", "l3-init-clkctrl:0008:24"),
746+
DT_CLK(NULL, "hsmmc2_fclk", "l3-init-clkctrl:0010:24"),
747+
DT_CLK(NULL, "iss_ctrlclk", "iss-clkctrl:0000:8"),
748+
DT_CLK(NULL, "mcasp_sync_mux_ck", "abe-clkctrl:0020:26"),
749+
DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe-clkctrl:0028:26"),
750+
DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe-clkctrl:0030:26"),
751+
DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe-clkctrl:0038:26"),
752+
DT_CLK(NULL, "mcbsp4_sync_mux_ck", "l4-per-clkctrl:00c0:26"),
753+
DT_CLK(NULL, "ocp2scp_usb_phy_phy_48m", "l3-init-clkctrl:00c0:8"),
754+
DT_CLK(NULL, "otg_60m_gfclk", "l3-init-clkctrl:0040:24"),
755+
DT_CLK(NULL, "per_mcbsp4_gfclk", "l4-per-clkctrl:00c0:24"),
756+
DT_CLK(NULL, "pmd_stm_clock_mux_ck", "emu-sys-clkctrl:0000:20"),
757+
DT_CLK(NULL, "pmd_trace_clk_mux_ck", "emu-sys-clkctrl:0000:22"),
758+
DT_CLK(NULL, "sgx_clk_mux", "l3-gfx-clkctrl:0000:24"),
759+
DT_CLK(NULL, "slimbus1_fclk_0", "abe-clkctrl:0040:8"),
760+
DT_CLK(NULL, "slimbus1_fclk_1", "abe-clkctrl:0040:9"),
761+
DT_CLK(NULL, "slimbus1_fclk_2", "abe-clkctrl:0040:10"),
762+
DT_CLK(NULL, "slimbus1_slimbus_clk", "abe-clkctrl:0040:11"),
763+
DT_CLK(NULL, "slimbus2_fclk_0", "l4-per-clkctrl:0118:8"),
764+
DT_CLK(NULL, "slimbus2_fclk_1", "l4-per-clkctrl:0118:9"),
765+
DT_CLK(NULL, "slimbus2_slimbus_clk", "l4-per-clkctrl:0118:10"),
766+
DT_CLK(NULL, "stm_clk_div_ck", "emu-sys-clkctrl:0000:27"),
767+
DT_CLK(NULL, "timer5_sync_mux", "abe-clkctrl:0048:24"),
768+
DT_CLK(NULL, "timer6_sync_mux", "abe-clkctrl:0050:24"),
769+
DT_CLK(NULL, "timer7_sync_mux", "abe-clkctrl:0058:24"),
770+
DT_CLK(NULL, "timer8_sync_mux", "abe-clkctrl:0060:24"),
771+
DT_CLK(NULL, "trace_clk_div_div_ck", "emu-sys-clkctrl:0000:24"),
772+
DT_CLK(NULL, "usb_host_hs_func48mclk", "l3-init-clkctrl:0038:15"),
773+
DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "l3-init-clkctrl:0038:13"),
774+
DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "l3-init-clkctrl:0038:14"),
775+
DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "l3-init-clkctrl:0038:11"),
776+
DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "l3-init-clkctrl:0038:12"),
777+
DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "l3-init-clkctrl:0038:8"),
778+
DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "l3-init-clkctrl:0038:9"),
779+
DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "l3_init-clkctrl:0038:10"),
780+
DT_CLK(NULL, "usb_otg_hs_xclk", "l3-init-clkctrl:0040:8"),
781+
DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "l3-init-clkctrl:0048:8"),
782+
DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "l3-init-clkctrl:0048:9"),
783+
DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "l3-init-clkctrl:0048:10"),
784+
DT_CLK(NULL, "utmi_p1_gfclk", "l3-init-clkctrl:0038:24"),
785+
DT_CLK(NULL, "utmi_p2_gfclk", "l3-init-clkctrl:0038:25"),
786786
{ .node_name = NULL },
787787
};
788788

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