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nxpfranklikwilczynski
nxpfrankli
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kwilczynski
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PCI: imx6: Introduce SoC specific callbacks for controlling REFCLK
Instead of using the switch case statement to enable/disable the reference clock handled by this driver itself, let's introduce a new callback enable_ref_clk() and define it for platforms that require it. This simplifies the code. Link: https://lore.kernel.org/linux-pci/20240729-pci2_upstream-v8-5-b68ee5ef2b4d@nxp.com Signed-off-by: Frank Li <Frank.Li@nxp.com> [kwilczynski: commit log] Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
1 parent d657ea2 commit 256867b

1 file changed

Lines changed: 51 additions & 60 deletions

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‎drivers/pci/controller/dwc/pci-imx6.c‎

Lines changed: 51 additions & 60 deletions
Original file line numberDiff line numberDiff line change
@@ -101,6 +101,7 @@ struct imx_pcie_drvdata {
101101
const u32 mode_mask[IMX_PCIE_MAX_INSTANCES];
102102
const struct pci_epc_features *epc_features;
103103
int (*init_phy)(struct imx_pcie *pcie);
104+
int (*enable_ref_clk)(struct imx_pcie *pcie, bool enable);
104105
};
105106

106107
struct imx_pcie {
@@ -582,77 +583,54 @@ static int imx_pcie_attach_pd(struct device *dev)
582583
return 0;
583584
}
584585

585-
static int imx_pcie_enable_ref_clk(struct imx_pcie *imx_pcie)
586+
static int imx6sx_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enable)
586587
{
587-
unsigned int offset;
588-
int ret = 0;
588+
if (enable)
589+
regmap_clear_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
590+
IMX6SX_GPR12_PCIE_TEST_POWERDOWN);
589591

590-
switch (imx_pcie->drvdata->variant) {
591-
case IMX6SX:
592-
regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
593-
IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0);
594-
break;
595-
case IMX6QP:
596-
case IMX6Q:
592+
return 0;
593+
}
594+
595+
static int imx6q_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enable)
596+
{
597+
if (enable) {
597598
/* power up core phy and enable ref clock */
598-
regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
599-
IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
599+
regmap_clear_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD);
600600
/*
601601
* the async reset input need ref clock to sync internally,
602602
* when the ref clock comes after reset, internal synced
603603
* reset time is too short, cannot meet the requirement.
604604
* add one ~10us delay here.
605605
*/
606606
usleep_range(10, 100);
607-
regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
608-
IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
609-
break;
610-
case IMX7D:
611-
case IMX95:
612-
case IMX95_EP:
613-
break;
614-
case IMX8MM:
615-
case IMX8MM_EP:
616-
case IMX8MQ:
617-
case IMX8MQ_EP:
618-
case IMX8MP:
619-
case IMX8MP_EP:
620-
offset = imx_pcie_grp_offset(imx_pcie);
621-
/*
622-
* Set the over ride low and enabled
623-
* make sure that REF_CLK is turned on.
624-
*/
625-
regmap_update_bits(imx_pcie->iomuxc_gpr, offset,
626-
IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE,
627-
0);
628-
regmap_update_bits(imx_pcie->iomuxc_gpr, offset,
629-
IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN,
630-
IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN);
631-
break;
607+
regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_REF_CLK_EN);
608+
} else {
609+
regmap_clear_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_REF_CLK_EN);
610+
regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD);
632611
}
633612

634-
return ret;
613+
return 0;
635614
}
636615

637-
static void imx_pcie_disable_ref_clk(struct imx_pcie *imx_pcie)
616+
static int imx8mm_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enable)
638617
{
639-
switch (imx_pcie->drvdata->variant) {
640-
case IMX6QP:
641-
case IMX6Q:
642-
regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
643-
IMX6Q_GPR1_PCIE_REF_CLK_EN, 0);
644-
regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
645-
IMX6Q_GPR1_PCIE_TEST_PD,
646-
IMX6Q_GPR1_PCIE_TEST_PD);
647-
break;
648-
case IMX7D:
649-
regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
650-
IMX7D_GPR12_PCIE_PHY_REFCLK_SEL,
651-
IMX7D_GPR12_PCIE_PHY_REFCLK_SEL);
652-
break;
653-
default:
654-
break;
618+
int offset = imx_pcie_grp_offset(imx_pcie);
619+
620+
if (enable) {
621+
regmap_clear_bits(imx_pcie->iomuxc_gpr, offset, IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE);
622+
regmap_set_bits(imx_pcie->iomuxc_gpr, offset, IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN);
655623
}
624+
625+
return 0;
626+
}
627+
628+
static int imx7d_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enable)
629+
{
630+
if (!enable)
631+
regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
632+
IMX7D_GPR12_PCIE_PHY_REFCLK_SEL);
633+
return 0;
656634
}
657635

658636
static int imx_pcie_clk_enable(struct imx_pcie *imx_pcie)
@@ -665,10 +643,12 @@ static int imx_pcie_clk_enable(struct imx_pcie *imx_pcie)
665643
if (ret)
666644
return ret;
667645

668-
ret = imx_pcie_enable_ref_clk(imx_pcie);
669-
if (ret) {
670-
dev_err(dev, "unable to enable pcie ref clock\n");
671-
goto err_ref_clk;
646+
if (imx_pcie->drvdata->enable_ref_clk) {
647+
ret = imx_pcie->drvdata->enable_ref_clk(imx_pcie, true);
648+
if (ret) {
649+
dev_err(dev, "Failed to enable PCIe REFCLK\n");
650+
goto err_ref_clk;
651+
}
672652
}
673653

674654
/* allow the clocks to stabilize */
@@ -683,7 +663,8 @@ static int imx_pcie_clk_enable(struct imx_pcie *imx_pcie)
683663

684664
static void imx_pcie_clk_disable(struct imx_pcie *imx_pcie)
685665
{
686-
imx_pcie_disable_ref_clk(imx_pcie);
666+
if (imx_pcie->drvdata->enable_ref_clk)
667+
imx_pcie->drvdata->enable_ref_clk(imx_pcie, false);
687668
clk_bulk_disable_unprepare(imx_pcie->drvdata->clks_cnt, imx_pcie->clks);
688669
}
689670

@@ -1459,6 +1440,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
14591440
.mode_off[0] = IOMUXC_GPR12,
14601441
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
14611442
.init_phy = imx_pcie_init_phy,
1443+
.enable_ref_clk = imx6q_pcie_enable_ref_clk,
14621444
},
14631445
[IMX6SX] = {
14641446
.variant = IMX6SX,
@@ -1473,6 +1455,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
14731455
.mode_off[0] = IOMUXC_GPR12,
14741456
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
14751457
.init_phy = imx6sx_pcie_init_phy,
1458+
.enable_ref_clk = imx6sx_pcie_enable_ref_clk,
14761459
},
14771460
[IMX6QP] = {
14781461
.variant = IMX6QP,
@@ -1488,6 +1471,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
14881471
.mode_off[0] = IOMUXC_GPR12,
14891472
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
14901473
.init_phy = imx_pcie_init_phy,
1474+
.enable_ref_clk = imx6q_pcie_enable_ref_clk,
14911475
},
14921476
[IMX7D] = {
14931477
.variant = IMX7D,
@@ -1500,6 +1484,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
15001484
.mode_off[0] = IOMUXC_GPR12,
15011485
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
15021486
.init_phy = imx7d_pcie_init_phy,
1487+
.enable_ref_clk = imx7d_pcie_enable_ref_clk,
15031488
},
15041489
[IMX8MQ] = {
15051490
.variant = IMX8MQ,
@@ -1513,6 +1498,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
15131498
.mode_off[1] = IOMUXC_GPR12,
15141499
.mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE,
15151500
.init_phy = imx8mq_pcie_init_phy,
1501+
.enable_ref_clk = imx8mm_pcie_enable_ref_clk,
15161502
},
15171503
[IMX8MM] = {
15181504
.variant = IMX8MM,
@@ -1524,6 +1510,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
15241510
.clks_cnt = ARRAY_SIZE(imx8mm_clks),
15251511
.mode_off[0] = IOMUXC_GPR12,
15261512
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
1513+
.enable_ref_clk = imx8mm_pcie_enable_ref_clk,
15271514
},
15281515
[IMX8MP] = {
15291516
.variant = IMX8MP,
@@ -1535,6 +1522,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
15351522
.clks_cnt = ARRAY_SIZE(imx8mm_clks),
15361523
.mode_off[0] = IOMUXC_GPR12,
15371524
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
1525+
.enable_ref_clk = imx8mm_pcie_enable_ref_clk,
15381526
},
15391527
[IMX95] = {
15401528
.variant = IMX95,
@@ -1561,6 +1549,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
15611549
.mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE,
15621550
.epc_features = &imx8m_pcie_epc_features,
15631551
.init_phy = imx8mq_pcie_init_phy,
1552+
.enable_ref_clk = imx8mm_pcie_enable_ref_clk,
15641553
},
15651554
[IMX8MM_EP] = {
15661555
.variant = IMX8MM_EP,
@@ -1573,6 +1562,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
15731562
.mode_off[0] = IOMUXC_GPR12,
15741563
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
15751564
.epc_features = &imx8m_pcie_epc_features,
1565+
.enable_ref_clk = imx8mm_pcie_enable_ref_clk,
15761566
},
15771567
[IMX8MP_EP] = {
15781568
.variant = IMX8MP_EP,
@@ -1585,6 +1575,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
15851575
.mode_off[0] = IOMUXC_GPR12,
15861576
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
15871577
.epc_features = &imx8m_pcie_epc_features,
1578+
.enable_ref_clk = imx8mm_pcie_enable_ref_clk,
15881579
},
15891580
[IMX95_EP] = {
15901581
.variant = IMX95_EP,

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