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Xiaojian Dualexdeucher
Xiaojian Du
authored and
alexdeucher
committed
drm/amdgpu: add files for PSP 13.0.4
This patch will add files for PSP 13.0.4. Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com> Reviewed-by: Tim Huang <Tim.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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‎drivers/gpu/drm/amd/amdgpu/psp_v13_0_4.c‎

Lines changed: 387 additions & 0 deletions
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/*
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* Copyright 2020 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "amdgpu.h"
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#include "amdgpu_psp.h"
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#include "amdgpu_ucode.h"
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#include "soc15_common.h"
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#include "psp_v13_0_4.h"
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#include "mp/mp_13_0_4_offset.h"
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#include "mp/mp_13_0_4_sh_mask.h"
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MODULE_FIRMWARE("amdgpu/psp_13_0_4_toc.bin");
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MODULE_FIRMWARE("amdgpu/psp_13_0_4_ta.bin");
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static int psp_v13_0_4_init_microcode(struct psp_context *psp)
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{
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struct amdgpu_device *adev = psp->adev;
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const char *chip_name;
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char ucode_prefix[30];
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int err = 0;
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switch (adev->ip_versions[MP0_HWIP][0]) {
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case IP_VERSION(13, 0, 4):
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amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix));
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chip_name = ucode_prefix;
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break;
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default:
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BUG();
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}
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switch (adev->ip_versions[MP0_HWIP][0]) {
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case IP_VERSION(13, 0, 4):
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err = psp_init_toc_microcode(psp, chip_name);
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if (err)
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return err;
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err = psp_init_ta_microcode(psp, chip_name);
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if (err)
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return err;
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break;
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default:
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BUG();
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}
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return 0;
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}
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static bool psp_v13_0_4_is_sos_alive(struct psp_context *psp)
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{
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struct amdgpu_device *adev = psp->adev;
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uint32_t sol_reg;
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sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
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return sol_reg != 0x0;
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}
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static int psp_v13_0_4_wait_for_bootloader(struct psp_context *psp)
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{
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struct amdgpu_device *adev = psp->adev;
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int ret;
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int retry_loop;
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for (retry_loop = 0; retry_loop < 10; retry_loop++) {
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/* Wait for bootloader to signify that is
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ready having bit 31 of C2PMSG_35 set to 1 */
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ret = psp_wait_for(psp,
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SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
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0x80000000,
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0x80000000,
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false);
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if (ret == 0)
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return 0;
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}
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return ret;
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}
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static int psp_v13_0_4_bootloader_load_component(struct psp_context *psp,
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struct psp_bin_desc *bin_desc,
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enum psp_bootloader_cmd bl_cmd)
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{
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int ret;
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uint32_t psp_gfxdrv_command_reg = 0;
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struct amdgpu_device *adev = psp->adev;
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/* Check tOS sign of life register to confirm sys driver and sOS
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* are already been loaded.
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*/
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if (psp_v13_0_4_is_sos_alive(psp))
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return 0;
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ret = psp_v13_0_4_wait_for_bootloader(psp);
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if (ret)
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return ret;
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memset(psp->fw_pri_buf, 0, PSP_1_MEG);
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/* Copy PSP KDB binary to memory */
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memcpy(psp->fw_pri_buf, bin_desc->start_addr, bin_desc->size_bytes);
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/* Provide the PSP KDB to bootloader */
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WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
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(uint32_t)(psp->fw_pri_mc_addr >> 20));
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psp_gfxdrv_command_reg = bl_cmd;
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WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35,
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psp_gfxdrv_command_reg);
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ret = psp_v13_0_4_wait_for_bootloader(psp);
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return ret;
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}
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static int psp_v13_0_4_bootloader_load_kdb(struct psp_context *psp)
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{
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return psp_v13_0_4_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE);
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}
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static int psp_v13_0_4_bootloader_load_spl(struct psp_context *psp)
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{
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return psp_v13_0_4_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_TOS_SPL_TABLE);
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}
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static int psp_v13_0_4_bootloader_load_sysdrv(struct psp_context *psp)
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{
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return psp_v13_0_4_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV);
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}
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static int psp_v13_0_4_bootloader_load_soc_drv(struct psp_context *psp)
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{
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return psp_v13_0_4_bootloader_load_component(psp, &psp->soc_drv, PSP_BL__LOAD_SOCDRV);
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}
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static int psp_v13_0_4_bootloader_load_intf_drv(struct psp_context *psp)
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{
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return psp_v13_0_4_bootloader_load_component(psp, &psp->intf_drv, PSP_BL__LOAD_INTFDRV);
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}
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static int psp_v13_0_4_bootloader_load_dbg_drv(struct psp_context *psp)
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{
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return psp_v13_0_4_bootloader_load_component(psp, &psp->dbg_drv, PSP_BL__LOAD_DBGDRV);
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}
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static int psp_v13_0_4_bootloader_load_sos(struct psp_context *psp)
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{
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int ret;
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unsigned int psp_gfxdrv_command_reg = 0;
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struct amdgpu_device *adev = psp->adev;
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/* Check sOS sign of life register to confirm sys driver and sOS
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* are already been loaded.
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*/
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if (psp_v13_0_4_is_sos_alive(psp))
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return 0;
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ret = psp_v13_0_4_wait_for_bootloader(psp);
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if (ret)
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return ret;
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memset(psp->fw_pri_buf, 0, PSP_1_MEG);
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/* Copy Secure OS binary to PSP memory */
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memcpy(psp->fw_pri_buf, psp->sos.start_addr, psp->sos.size_bytes);
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/* Provide the PSP secure OS to bootloader */
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WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
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(uint32_t)(psp->fw_pri_mc_addr >> 20));
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psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
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WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35,
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psp_gfxdrv_command_reg);
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/* there might be handshake issue with hardware which needs delay */
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mdelay(20);
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ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81),
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RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81),
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0, true);
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return ret;
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}
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static int psp_v13_0_4_ring_init(struct psp_context *psp,
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enum psp_ring_type ring_type)
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{
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int ret = 0;
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struct psp_ring *ring;
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struct amdgpu_device *adev = psp->adev;
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ring = &psp->km_ring;
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ring->ring_type = ring_type;
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/* allocate 4k Page of Local Frame Buffer memory for ring */
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ring->ring_size = 0x1000;
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ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
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AMDGPU_GEM_DOMAIN_VRAM,
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&adev->firmware.rbuf,
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&ring->ring_mem_mc_addr,
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(void **)&ring->ring_mem);
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if (ret) {
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ring->ring_size = 0;
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return ret;
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}
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return 0;
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}
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static int psp_v13_0_4_ring_stop(struct psp_context *psp,
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enum psp_ring_type ring_type)
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{
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int ret = 0;
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struct amdgpu_device *adev = psp->adev;
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if (amdgpu_sriov_vf(adev)) {
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/* Write the ring destroy command*/
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WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
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GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
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/* there might be handshake issue with hardware which needs delay */
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mdelay(20);
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/* Wait for response flag (bit 31) */
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ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
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0x80000000, 0x80000000, false);
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} else {
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/* Write the ring destroy command*/
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WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64,
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GFX_CTRL_CMD_ID_DESTROY_RINGS);
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/* there might be handshake issue with hardware which needs delay */
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mdelay(20);
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/* Wait for response flag (bit 31) */
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ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
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0x80000000, 0x80000000, false);
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}
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return ret;
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}
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static int psp_v13_0_4_ring_create(struct psp_context *psp,
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enum psp_ring_type ring_type)
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{
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int ret = 0;
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unsigned int psp_ring_reg = 0;
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struct psp_ring *ring = &psp->km_ring;
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struct amdgpu_device *adev = psp->adev;
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if (amdgpu_sriov_vf(adev)) {
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ret = psp_v13_0_4_ring_stop(psp, ring_type);
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if (ret) {
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DRM_ERROR("psp_v13_0_ring_stop_sriov failed!\n");
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return ret;
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}
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/* Write low address of the ring to C2PMSG_102 */
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psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
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WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, psp_ring_reg);
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/* Write high address of the ring to C2PMSG_103 */
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psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
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WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, psp_ring_reg);
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/* Write the ring initialization command to C2PMSG_101 */
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WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
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GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
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/* there might be handshake issue with hardware which needs delay */
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mdelay(20);
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/* Wait for response flag (bit 31) in C2PMSG_101 */
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ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
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0x80000000, 0x8000FFFF, false);
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} else {
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/* Wait for sOS ready for ring creation */
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ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
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0x80000000, 0x80000000, false);
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if (ret) {
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DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
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return ret;
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}
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/* Write low address of the ring to C2PMSG_69 */
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psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
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WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_69, psp_ring_reg);
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/* Write high address of the ring to C2PMSG_70 */
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psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
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WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_70, psp_ring_reg);
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/* Write size of ring to C2PMSG_71 */
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psp_ring_reg = ring->ring_size;
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WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_71, psp_ring_reg);
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/* Write the ring initialization command to C2PMSG_64 */
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psp_ring_reg = ring_type;
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psp_ring_reg = psp_ring_reg << 16;
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WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, psp_ring_reg);
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/* there might be handshake issue with hardware which needs delay */
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mdelay(20);
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/* Wait for response flag (bit 31) in C2PMSG_64 */
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ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
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0x80000000, 0x8000FFFF, false);
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}
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return ret;
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}
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static int psp_v13_0_4_ring_destroy(struct psp_context *psp,
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enum psp_ring_type ring_type)
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{
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int ret = 0;
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struct psp_ring *ring = &psp->km_ring;
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struct amdgpu_device *adev = psp->adev;
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ret = psp_v13_0_4_ring_stop(psp, ring_type);
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if (ret)
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DRM_ERROR("Fail to stop psp ring\n");
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amdgpu_bo_free_kernel(&adev->firmware.rbuf,
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&ring->ring_mem_mc_addr,
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(void **)&ring->ring_mem);
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return ret;
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}
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static uint32_t psp_v13_0_4_ring_get_wptr(struct psp_context *psp)
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{
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uint32_t data;
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struct amdgpu_device *adev = psp->adev;
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if (amdgpu_sriov_vf(adev))
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data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102);
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else
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data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67);
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return data;
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}
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static void psp_v13_0_4_ring_set_wptr(struct psp_context *psp, uint32_t value)
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{
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struct amdgpu_device *adev = psp->adev;
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if (amdgpu_sriov_vf(adev)) {
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WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, value);
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WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
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GFX_CTRL_CMD_ID_CONSUME_CMD);
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} else
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WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, value);
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}
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static const struct psp_funcs psp_v13_0_4_funcs = {
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.init_microcode = psp_v13_0_4_init_microcode,
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.bootloader_load_kdb = psp_v13_0_4_bootloader_load_kdb,
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.bootloader_load_spl = psp_v13_0_4_bootloader_load_spl,
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.bootloader_load_sysdrv = psp_v13_0_4_bootloader_load_sysdrv,
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.bootloader_load_soc_drv = psp_v13_0_4_bootloader_load_soc_drv,
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.bootloader_load_intf_drv = psp_v13_0_4_bootloader_load_intf_drv,
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.bootloader_load_dbg_drv = psp_v13_0_4_bootloader_load_dbg_drv,
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.bootloader_load_sos = psp_v13_0_4_bootloader_load_sos,
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.ring_init = psp_v13_0_4_ring_init,
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.ring_create = psp_v13_0_4_ring_create,
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.ring_stop = psp_v13_0_4_ring_stop,
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.ring_destroy = psp_v13_0_4_ring_destroy,
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.ring_get_wptr = psp_v13_0_4_ring_get_wptr,
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.ring_set_wptr = psp_v13_0_4_ring_set_wptr,
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};
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void psp_v13_0_4_set_psp_funcs(struct psp_context *psp)
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{
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psp->funcs = &psp_v13_0_4_funcs;
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}

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