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ALSA: emu10k1: fixup DSP defines
Firstly, fix the distribution between public and private headers. Otherwise, some of the already public macros wouldn't actually work, and the SNDRV_EMU10K1_IOCTL_DBG_READ result for Audigy would be useless. Secondly, add condition code registers for Audigy. These are just aliases for selected constant registers, and thus are generation- specific. At least A_CC_REG_ZERO is actually correct ... Finally, shuffle around some defines to more logical places while at it, and fix up some more comments. Signed-off-by: Oswald Buddenhagen <oswald.buddenhagen@gmx.de> Link: https://lore.kernel.org/r/20230422161021.1143903-7-oswald.buddenhagen@gmx.de Signed-off-by: Takashi Iwai <tiwai@suse.de>
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Lines changed: 99 additions & 91 deletions

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‎include/sound/emu10k1.h‎

Lines changed: 6 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -704,18 +704,15 @@
704704

705705
#define GPSCS 0x51 /* General Purpose SPDIF channel status register */
706706

707+
// Corresponding EMU10K1_DBG_* constants are in the public header
707708
#define DBG 0x52
708709

709710
#define A_SPSC 0x52 /* S/PDIF Input C Channel Status */
710711

711712
#define REG53 0x53 /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */
712713

713-
#define A_DBG 0x53
714-
#define A_DBG_SINGLE_STEP 0x00020000 /* Set to zero to start dsp */
715-
#define A_DBG_ZC 0x40000000 /* zero tram counter */
716-
#define A_DBG_STEP_ADDR 0x000003ff
717-
#define A_DBG_SATURATION_OCCURED 0x20000000
718-
#define A_DBG_SATURATION_ADDR 0x0ffc0000
714+
// Corresponding A_DBG_* constants are in the public header
715+
#define A_DBG 0x53
719716

720717
// NOTE: 0x54,55,56: 64-bit (split over voices 0 & 1)
721718
#define SPCS0 0x54 /* SPDIF output Channel Status 0 register */
@@ -908,45 +905,14 @@
908905
#define A_FXRT_CHANNELD 0x3f000000
909906

910907
/* 0x7f: Not used */
911-
/* Each FX general purpose register is 32 bits in length, all bits are used */
912-
#define FXGPREGBASE 0x100 /* FX general purpose registers base */
913-
#define A_FXGPREGBASE 0x400 /* Audigy GPRs, 0x400 to 0x5ff */
914-
915-
#define A_TANKMEMCTLREGBASE 0x100 /* Tank memory control registers base - only for Audigy */
916-
#define A_TANKMEMCTLREG_MASK 0x1f /* only 5 bits used - only for Audigy */
917-
918-
/* Tank audio data is logarithmically compressed down to 16 bits before writing to TRAM and is */
919-
/* decompressed back to 20 bits on a read. There are a total of 160 locations, the last 32 */
920-
/* locations are for external TRAM. */
921-
#define TANKMEMDATAREGBASE 0x200 /* Tank memory data registers base */
922-
#define TANKMEMDATAREG_MASK 0x000fffff /* 20 bit tank audio data field */
923-
924-
/* Combined address field and memory opcode or flag field. 160 locations, last 32 are external */
925-
#define TANKMEMADDRREGBASE 0x300 /* Tank memory address registers base */
926-
#define TANKMEMADDRREG_ADDR_MASK 0x000fffff /* 20 bit tank address field */
927-
#define TANKMEMADDRREG_CLEAR 0x00800000 /* Clear tank memory */
928-
#define TANKMEMADDRREG_ALIGN 0x00400000 /* Align read or write relative to tank access */
929-
#define TANKMEMADDRREG_WRITE 0x00200000 /* Write to tank memory */
930-
#define TANKMEMADDRREG_READ 0x00100000 /* Read from tank memory */
931908

932-
#define MICROCODEBASE 0x400 /* Microcode data base address */
909+
/* The public header defines the GPR and TRAM base addresses that
910+
* are valid for _both_ CPU and DSP addressing. */
933911

934912
/* Each DSP microcode instruction is mapped into 2 doublewords */
935913
/* NOTE: When writing, always write the LO doubleword first. Reads can be in either order. */
936-
#define LOWORD_OPX_MASK 0x000ffc00 /* Instruction operand X */
937-
#define LOWORD_OPY_MASK 0x000003ff /* Instruction operand Y */
938-
#define HIWORD_OPCODE_MASK 0x00f00000 /* Instruction opcode */
939-
#define HIWORD_RESULT_MASK 0x000ffc00 /* Instruction result */
940-
#define HIWORD_OPA_MASK 0x000003ff /* Instruction operand A */
941-
942-
943-
/* Audigy Soundcard have a different instruction format */
914+
#define MICROCODEBASE 0x400 /* Microcode data base address */
944915
#define A_MICROCODEBASE 0x600
945-
#define A_LOWORD_OPY_MASK 0x000007ff
946-
#define A_LOWORD_OPX_MASK 0x007ff000
947-
#define A_HIWORD_OPCODE_MASK 0x0f000000
948-
#define A_HIWORD_RESULT_MASK 0x007ff000
949-
#define A_HIWORD_OPA_MASK 0x000007ff
950916

951917

952918
/************************************************************************************************/

‎include/uapi/sound/emu10k1.h‎

Lines changed: 93 additions & 51 deletions
Original file line numberDiff line numberDiff line change
@@ -43,13 +43,36 @@
4343
#define iINTERP 0x0e /* R = A + (X * (Y - A) >> 31) ; saturation */
4444
#define iSKIP 0x0f /* R = A (cc_reg), X (count), Y (cc_test) */
4545

46+
#define LOWORD_OPX_MASK 0x000ffc00 /* Instruction operand X */
47+
#define LOWORD_OPY_MASK 0x000003ff /* Instruction operand Y */
48+
#define HIWORD_OPCODE_MASK 0x00f00000 /* Instruction opcode */
49+
#define HIWORD_RESULT_MASK 0x000ffc00 /* Instruction result */
50+
#define HIWORD_OPA_MASK 0x000003ff /* Instruction operand A */
51+
52+
/* Audigy Soundcards have a different instruction format */
53+
#define A_LOWORD_OPX_MASK 0x007ff000
54+
#define A_LOWORD_OPY_MASK 0x000007ff
55+
#define A_HIWORD_OPCODE_MASK 0x0f000000
56+
#define A_HIWORD_RESULT_MASK 0x007ff000
57+
#define A_HIWORD_OPA_MASK 0x000007ff
58+
4659
/* GPRs */
4760
#define FXBUS(x) (0x00 + (x)) /* x = 0x00 - 0x0f */
4861
#define EXTIN(x) (0x10 + (x)) /* x = 0x00 - 0x0f */
4962
#define EXTOUT(x) (0x20 + (x)) /* x = 0x00 - 0x0f physical outs -> FXWC low 16 bits */
5063
#define FXBUS2(x) (0x30 + (x)) /* x = 0x00 - 0x0f copies of fx buses for capture -> FXWC high 16 bits */
5164
/* NB: 0x31 and 0x32 are shared with Center/LFE on SB live 5.1 */
5265

66+
#define A_FXBUS(x) (0x00 + (x)) /* x = 0x00 - 0x3f FX buses */
67+
#define A_EXTIN(x) (0x40 + (x)) /* x = 0x00 - 0x0f physical ins */
68+
#define A_P16VIN(x) (0x50 + (x)) /* x = 0x00 - 0x0f p16v ins (A2 only) "EMU32 inputs" */
69+
#define A_EXTOUT(x) (0x60 + (x)) /* x = 0x00 - 0x1f physical outs -> A_FXWC1 0x79-7f unknown */
70+
#define A_FXBUS2(x) (0x80 + (x)) /* x = 0x00 - 0x1f extra outs used for EFX capture -> A_FXWC2 */
71+
#define A_EMU32OUTH(x) (0xa0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_10 - _1F" */
72+
#define A_EMU32OUTL(x) (0xb0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_01 - _0F" */
73+
#define A3_EMU32IN(x) (0x160 + (x)) /* x = 0x00 - 0x1f "EMU32_IN_00 - _1F" - Only when .device = 0x0008 */
74+
#define A3_EMU32OUT(x) (0x1E0 + (x)) /* x = 0x00 - 0x1f "EMU32_OUT_00 - _1F" - Only when .device = 0x0008 */
75+
5376
#define C_00000000 0x40
5477
#define C_00000001 0x41
5578
#define C_00000002 0x42
@@ -78,30 +101,73 @@
78101
#define GPR_NOISE1 0x59 /* noise source */
79102
#define GPR_IRQ 0x5a /* IRQ register */
80103
#define GPR_DBAC 0x5b /* TRAM Delay Base Address Counter */
104+
105+
/* Audigy constants */
106+
#define A_C_00000000 0xc0
107+
#define A_C_00000001 0xc1
108+
#define A_C_00000002 0xc2
109+
#define A_C_00000003 0xc3
110+
#define A_C_00000004 0xc4
111+
#define A_C_00000008 0xc5
112+
#define A_C_00000010 0xc6
113+
#define A_C_00000020 0xc7
114+
#define A_C_00000100 0xc8
115+
#define A_C_00010000 0xc9
116+
#define A_C_00000800 0xca
117+
#define A_C_10000000 0xcb
118+
#define A_C_20000000 0xcc
119+
#define A_C_40000000 0xcd
120+
#define A_C_80000000 0xce
121+
#define A_C_7fffffff 0xcf
122+
#define A_C_ffffffff 0xd0
123+
#define A_C_fffffffe 0xd1
124+
#define A_C_c0000000 0xd2
125+
#define A_C_4f1bbcdc 0xd3
126+
#define A_C_5a7ef9db 0xd4
127+
#define A_C_00100000 0xd5
128+
#define A_GPR_ACCU 0xd6 /* ACCUM, accumulator */
129+
#define A_GPR_COND 0xd7 /* CCR, condition register */
130+
#define A_GPR_NOISE0 0xd8 /* noise source */
131+
#define A_GPR_NOISE1 0xd9 /* noise source */
132+
#define A_GPR_IRQ 0xda /* IRQ register */
133+
#define A_GPR_DBAC 0xdb /* TRAM Delay Base Address Counter - internal */
134+
#define A_GPR_DBACE 0xde /* TRAM Delay Base Address Counter - external */
135+
136+
/* Each FX general purpose register is 32 bits in length, all bits are used */
137+
#define FXGPREGBASE 0x100 /* FX general purpose registers base */
138+
#define A_FXGPREGBASE 0x400 /* Audigy GPRs, 0x400 to 0x5ff */
139+
140+
#define A_TANKMEMCTLREGBASE 0x100 /* Tank memory control registers base - only for Audigy */
141+
#define A_TANKMEMCTLREG_MASK 0x1f /* only 5 bits used - only for Audigy */
142+
143+
/* Tank audio data is logarithmically compressed down to 16 bits before writing to TRAM and is */
144+
/* decompressed back to 20 bits on a read. There are a total of 160 locations, the last 32 */
145+
/* locations are for external TRAM. */
146+
#define TANKMEMDATAREGBASE 0x200 /* Tank memory data registers base */
147+
#define TANKMEMDATAREG_MASK 0x000fffff /* 20 bit tank audio data field */
148+
149+
/* Combined address field and memory opcode or flag field. 160 locations, last 32 are external */
150+
#define TANKMEMADDRREGBASE 0x300 /* Tank memory address registers base */
151+
#define TANKMEMADDRREG_ADDR_MASK 0x000fffff /* 20 bit tank address field */
152+
#define TANKMEMADDRREG_CLEAR 0x00800000 /* Clear tank memory */
153+
#define TANKMEMADDRREG_ALIGN 0x00400000 /* Align read or write relative to tank access */
154+
#define TANKMEMADDRREG_WRITE 0x00200000 /* Write to tank memory */
155+
#define TANKMEMADDRREG_READ 0x00100000 /* Read from tank memory */
156+
81157
#define GPR(x) (FXGPREGBASE + (x)) /* free GPRs: x = 0x00 - 0xff */
82158
#define ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x)) /* x = 0x00 - 0x7f */
83159
#define ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0x80 + (x)) /* x = 0x00 - 0x1f */
84160
#define ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x)) /* x = 0x00 - 0x7f */
85161
#define ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x80 + (x)) /* x = 0x00 - 0x1f */
86162

163+
#define A_GPR(x) (A_FXGPREGBASE + (x))
87164
#define A_ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */
88165
#define A_ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */
89166
#define A_ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */
90167
#define A_ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */
91168
#define A_ITRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */
92169
#define A_ETRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */
93170

94-
#define A_FXBUS(x) (0x00 + (x)) /* x = 0x00 - 0x3f FX buses */
95-
#define A_EXTIN(x) (0x40 + (x)) /* x = 0x00 - 0x0f physical ins */
96-
#define A_P16VIN(x) (0x50 + (x)) /* x = 0x00 - 0x0f p16v ins (A2 only) "EMU32 inputs" */
97-
#define A_EXTOUT(x) (0x60 + (x)) /* x = 0x00 - 0x1f physical outs -> A_FXWC1 0x79-7f unknown */
98-
#define A_FXBUS2(x) (0x80 + (x)) /* x = 0x00 - 0x1f extra outs used for EFX capture -> A_FXWC2 */
99-
#define A_EMU32OUTH(x) (0xa0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_10 - _1F" - ??? */
100-
#define A_EMU32OUTL(x) (0xb0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_1 - _F" - ??? */
101-
#define A3_EMU32IN(x) (0x160 + (x)) /* x = 0x00 - 0x3f "EMU32_IN_00 - _3F" - Only when .device = 0x0008 */
102-
#define A3_EMU32OUT(x) (0x1E0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_00 - _3F" - Only when .device = 0x0008 */
103-
#define A_GPR(x) (A_FXGPREGBASE + (x))
104-
105171
/* cc_reg constants */
106172
#define CC_REG_NORMALIZED C_00000001
107173
#define CC_REG_BORROW C_00000002
@@ -110,6 +176,13 @@
110176
#define CC_REG_SATURATE C_00000010
111177
#define CC_REG_NONZERO C_00000100
112178

179+
#define A_CC_REG_NORMALIZED A_C_00000001
180+
#define A_CC_REG_BORROW A_C_00000002
181+
#define A_CC_REG_MINUS A_C_00000004
182+
#define A_CC_REG_ZERO A_C_00000008
183+
#define A_CC_REG_SATURATE A_C_00000010
184+
#define A_CC_REG_NONZERO A_C_00000100
185+
113186
/* FX buses */
114187
// These are arbitrary mappings; our DSP code simply expects
115188
// the config files to route the channels this way.
@@ -203,38 +276,7 @@
203276
#define A_EXTOUT_ADC_CAP_R 0x17 /* right */
204277
#define A_EXTOUT_MIC_CAP 0x18 /* Mic capture buffer */
205278

206-
/* Audigy constants */
207-
#define A_C_00000000 0xc0
208-
#define A_C_00000001 0xc1
209-
#define A_C_00000002 0xc2
210-
#define A_C_00000003 0xc3
211-
#define A_C_00000004 0xc4
212-
#define A_C_00000008 0xc5
213-
#define A_C_00000010 0xc6
214-
#define A_C_00000020 0xc7
215-
#define A_C_00000100 0xc8
216-
#define A_C_00010000 0xc9
217-
#define A_C_00000800 0xca
218-
#define A_C_10000000 0xcb
219-
#define A_C_20000000 0xcc
220-
#define A_C_40000000 0xcd
221-
#define A_C_80000000 0xce
222-
#define A_C_7fffffff 0xcf
223-
#define A_C_ffffffff 0xd0
224-
#define A_C_fffffffe 0xd1
225-
#define A_C_c0000000 0xd2
226-
#define A_C_4f1bbcdc 0xd3
227-
#define A_C_5a7ef9db 0xd4
228-
#define A_C_00100000 0xd5
229-
#define A_GPR_ACCU 0xd6 /* ACCUM, accumulator */
230-
#define A_GPR_COND 0xd7 /* CCR, condition register */
231-
#define A_GPR_NOISE0 0xd8 /* noise source */
232-
#define A_GPR_NOISE1 0xd9 /* noise source */
233-
#define A_GPR_IRQ 0xda /* IRQ register */
234-
#define A_GPR_DBAC 0xdb /* TRAM Delay Base Address Counter - internal */
235-
#define A_GPR_DBACE 0xde /* TRAM Delay Base Address Counter - external */
236-
237-
/* definitions for debug register */
279+
/* Definitions for debug register. Note that these are for emu10k1 ONLY. */
238280
#define EMU10K1_DBG_ZC 0x80000000 /* zero tram counter */
239281
#define EMU10K1_DBG_SATURATION_OCCURED 0x02000000 /* saturation control */
240282
#define EMU10K1_DBG_SATURATION_ADDR 0x01ff0000 /* saturation address */
@@ -243,14 +285,14 @@
243285
#define EMU10K1_DBG_CONDITION_CODE 0x00003e00 /* condition code */
244286
#define EMU10K1_DBG_SINGLE_STEP_ADDR 0x000001ff /* single step address */
245287

246-
/* tank memory address line */
247-
#ifndef __KERNEL__
248-
#define TANKMEMADDRREG_ADDR_MASK 0x000fffff /* 20 bit tank address field */
249-
#define TANKMEMADDRREG_CLEAR 0x00800000 /* Clear tank memory */
250-
#define TANKMEMADDRREG_ALIGN 0x00400000 /* Align read or write relative to tank access */
251-
#define TANKMEMADDRREG_WRITE 0x00200000 /* Write to tank memory */
252-
#define TANKMEMADDRREG_READ 0x00100000 /* Read from tank memory */
253-
#endif
288+
/* Definitions for emu10k2 debug register. */
289+
#define A_DBG_ZC 0x40000000 /* zero tram counter */
290+
#define A_DBG_SATURATION_OCCURED 0x20000000
291+
#define A_DBG_SATURATION_ADDR 0x0ffc0000
292+
#define A_DBG_SINGLE_STEP 0x00020000 /* Set to zero to start dsp */
293+
#define A_DBG_STEP 0x00010000
294+
#define A_DBG_CONDITION_CODE 0x0000f800
295+
#define A_DBG_STEP_ADDR 0x000003ff
254296

255297
struct snd_emu10k1_fx8010_info {
256298
unsigned int internal_tram_size; /* in samples */

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