Skip to content

Commit 26ad971

Browse files
esmilbebarino
esmil
authored and
bebarino
committed
clk: starfive: jh7100: Make hw clock implementation reusable
The JH7100 has additional audio and video clocks at different memory ranges, but they use the same register layout. Add a header and export the starfive_jh7100_clk_ops function so the clock implementation can be reused by drivers handling these clocks. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Link: https://lore.kernel.org/r/20220126173953.1016706-6-kernel@esmil.dk Signed-off-by: Stephen Boyd <sboyd@kernel.org>
1 parent c31b32f commit 26ad971

2 files changed

Lines changed: 104 additions & 89 deletions

File tree

‎drivers/clk/starfive/clk-starfive-jh7100.c‎

Lines changed: 7 additions & 89 deletions
Original file line numberDiff line numberDiff line change
@@ -20,83 +20,15 @@
2020

2121
#include <dt-bindings/clock/starfive-jh7100.h>
2222

23+
#include "clk-starfive-jh7100.h"
24+
2325
/* external clocks */
2426
#define JH7100_CLK_OSC_SYS (JH7100_CLK_END + 0)
2527
#define JH7100_CLK_OSC_AUD (JH7100_CLK_END + 1)
2628
#define JH7100_CLK_GMAC_RMII_REF (JH7100_CLK_END + 2)
2729
#define JH7100_CLK_GMAC_GR_MII_RX (JH7100_CLK_END + 3)
2830

29-
/* register fields */
30-
#define JH7100_CLK_ENABLE BIT(31)
31-
#define JH7100_CLK_INVERT BIT(30)
32-
#define JH7100_CLK_MUX_MASK GENMASK(27, 24)
33-
#define JH7100_CLK_MUX_SHIFT 24
34-
#define JH7100_CLK_DIV_MASK GENMASK(23, 0)
35-
#define JH7100_CLK_FRAC_MASK GENMASK(15, 8)
36-
#define JH7100_CLK_FRAC_SHIFT 8
37-
#define JH7100_CLK_INT_MASK GENMASK(7, 0)
38-
39-
/* fractional divider min/max */
40-
#define JH7100_CLK_FRAC_MIN 100UL
41-
#define JH7100_CLK_FRAC_MAX 25599UL
42-
43-
/* clock data */
44-
#define JH7100_GATE(_idx, _name, _flags, _parent) [_idx] = { \
45-
.name = _name, \
46-
.flags = CLK_SET_RATE_PARENT | (_flags), \
47-
.max = JH7100_CLK_ENABLE, \
48-
.parents = { [0] = _parent }, \
49-
}
50-
51-
#define JH7100__DIV(_idx, _name, _max, _parent) [_idx] = { \
52-
.name = _name, \
53-
.flags = 0, \
54-
.max = _max, \
55-
.parents = { [0] = _parent }, \
56-
}
57-
58-
#define JH7100_GDIV(_idx, _name, _flags, _max, _parent) [_idx] = { \
59-
.name = _name, \
60-
.flags = _flags, \
61-
.max = JH7100_CLK_ENABLE | (_max), \
62-
.parents = { [0] = _parent }, \
63-
}
64-
65-
#define JH7100_FDIV(_idx, _name, _parent) [_idx] = { \
66-
.name = _name, \
67-
.flags = 0, \
68-
.max = JH7100_CLK_FRAC_MAX, \
69-
.parents = { [0] = _parent }, \
70-
}
71-
72-
#define JH7100__MUX(_idx, _name, _nparents, ...) [_idx] = { \
73-
.name = _name, \
74-
.flags = 0, \
75-
.max = ((_nparents) - 1) << JH7100_CLK_MUX_SHIFT, \
76-
.parents = { __VA_ARGS__ }, \
77-
}
78-
79-
#define JH7100_GMUX(_idx, _name, _flags, _nparents, ...) [_idx] = { \
80-
.name = _name, \
81-
.flags = _flags, \
82-
.max = JH7100_CLK_ENABLE | \
83-
(((_nparents) - 1) << JH7100_CLK_MUX_SHIFT), \
84-
.parents = { __VA_ARGS__ }, \
85-
}
86-
87-
#define JH7100__INV(_idx, _name, _parent) [_idx] = { \
88-
.name = _name, \
89-
.flags = CLK_SET_RATE_PARENT, \
90-
.max = JH7100_CLK_INVERT, \
91-
.parents = { [0] = _parent }, \
92-
}
93-
94-
static const struct {
95-
const char *name;
96-
unsigned long flags;
97-
u32 max;
98-
u8 parents[4];
99-
} jh7100_clk_data[] __initconst = {
31+
static const struct jh7100_clk_data jh7100_clk_data[] __initconst = {
10032
JH7100__MUX(JH7100_CLK_CPUNDBUS_ROOT, "cpundbus_root", 4,
10133
JH7100_CLK_OSC_SYS,
10234
JH7100_CLK_PLL0_OUT,
@@ -337,21 +269,6 @@ static const struct {
337269
JH7100_GATE(JH7100_CLK_SYSERR_APB, "syserr_apb", 0, JH7100_CLK_APB2_BUS),
338270
};
339271

340-
struct jh7100_clk {
341-
struct clk_hw hw;
342-
unsigned int idx;
343-
unsigned int max_div;
344-
};
345-
346-
struct jh7100_clk_priv {
347-
/* protect clk enable and set rate/parent from happening at the same time */
348-
spinlock_t rmw_lock;
349-
struct device *dev;
350-
void __iomem *base;
351-
struct clk_hw *pll[3];
352-
struct jh7100_clk reg[JH7100_CLK_PLL0_OUT];
353-
};
354-
355272
static struct jh7100_clk *jh7100_clk_from(struct clk_hw *hw)
356273
{
357274
return container_of(hw, struct jh7100_clk, hw);
@@ -623,7 +540,7 @@ static const struct clk_ops jh7100_clk_inv_ops = {
623540
.debug_init = jh7100_clk_debug_init,
624541
};
625542

626-
static const struct clk_ops *__init jh7100_clk_ops(u32 max)
543+
const struct clk_ops *starfive_jh7100_clk_ops(u32 max)
627544
{
628545
if (max & JH7100_CLK_DIV_MASK) {
629546
if (max & JH7100_CLK_ENABLE)
@@ -644,6 +561,7 @@ static const struct clk_ops *__init jh7100_clk_ops(u32 max)
644561

645562
return &jh7100_clk_inv_ops;
646563
}
564+
EXPORT_SYMBOL_GPL(starfive_jh7100_clk_ops);
647565

648566
static struct clk_hw *jh7100_clk_get(struct of_phandle_args *clkspec, void *data)
649567
{
@@ -665,7 +583,7 @@ static int __init clk_starfive_jh7100_probe(struct platform_device *pdev)
665583
unsigned int idx;
666584
int ret;
667585

668-
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
586+
priv = devm_kzalloc(&pdev->dev, struct_size(priv, reg, JH7100_CLK_PLL0_OUT), GFP_KERNEL);
669587
if (!priv)
670588
return -ENOMEM;
671589

@@ -695,7 +613,7 @@ static int __init clk_starfive_jh7100_probe(struct platform_device *pdev)
695613
struct clk_parent_data parents[4] = {};
696614
struct clk_init_data init = {
697615
.name = jh7100_clk_data[idx].name,
698-
.ops = jh7100_clk_ops(max),
616+
.ops = starfive_jh7100_clk_ops(max),
699617
.parent_data = parents,
700618
.num_parents = ((max & JH7100_CLK_MUX_MASK) >> JH7100_CLK_MUX_SHIFT) + 1,
701619
.flags = jh7100_clk_data[idx].flags,

‎drivers/clk/starfive/clk-starfive-jh7100.h‎

Lines changed: 97 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,97 @@
1+
/* SPDX-License-Identifier: GPL-2.0 */
2+
#ifndef __CLK_STARFIVE_JH7100_H
3+
#define __CLK_STARFIVE_JH7100_H
4+
5+
#include <linux/bits.h>
6+
#include <linux/clk-provider.h>
7+
8+
/* register fields */
9+
#define JH7100_CLK_ENABLE BIT(31)
10+
#define JH7100_CLK_INVERT BIT(30)
11+
#define JH7100_CLK_MUX_MASK GENMASK(27, 24)
12+
#define JH7100_CLK_MUX_SHIFT 24
13+
#define JH7100_CLK_DIV_MASK GENMASK(23, 0)
14+
#define JH7100_CLK_FRAC_MASK GENMASK(15, 8)
15+
#define JH7100_CLK_FRAC_SHIFT 8
16+
#define JH7100_CLK_INT_MASK GENMASK(7, 0)
17+
18+
/* fractional divider min/max */
19+
#define JH7100_CLK_FRAC_MIN 100UL
20+
#define JH7100_CLK_FRAC_MAX 25599UL
21+
22+
/* clock data */
23+
struct jh7100_clk_data {
24+
const char *name;
25+
unsigned long flags;
26+
u32 max;
27+
u8 parents[4];
28+
};
29+
30+
#define JH7100_GATE(_idx, _name, _flags, _parent) [_idx] = { \
31+
.name = _name, \
32+
.flags = CLK_SET_RATE_PARENT | (_flags), \
33+
.max = JH7100_CLK_ENABLE, \
34+
.parents = { [0] = _parent }, \
35+
}
36+
37+
#define JH7100__DIV(_idx, _name, _max, _parent) [_idx] = { \
38+
.name = _name, \
39+
.flags = 0, \
40+
.max = _max, \
41+
.parents = { [0] = _parent }, \
42+
}
43+
44+
#define JH7100_GDIV(_idx, _name, _flags, _max, _parent) [_idx] = { \
45+
.name = _name, \
46+
.flags = _flags, \
47+
.max = JH7100_CLK_ENABLE | (_max), \
48+
.parents = { [0] = _parent }, \
49+
}
50+
51+
#define JH7100_FDIV(_idx, _name, _parent) [_idx] = { \
52+
.name = _name, \
53+
.flags = 0, \
54+
.max = JH7100_CLK_FRAC_MAX, \
55+
.parents = { [0] = _parent }, \
56+
}
57+
58+
#define JH7100__MUX(_idx, _name, _nparents, ...) [_idx] = { \
59+
.name = _name, \
60+
.flags = 0, \
61+
.max = ((_nparents) - 1) << JH7100_CLK_MUX_SHIFT, \
62+
.parents = { __VA_ARGS__ }, \
63+
}
64+
65+
#define JH7100_GMUX(_idx, _name, _flags, _nparents, ...) [_idx] = { \
66+
.name = _name, \
67+
.flags = _flags, \
68+
.max = JH7100_CLK_ENABLE | \
69+
(((_nparents) - 1) << JH7100_CLK_MUX_SHIFT), \
70+
.parents = { __VA_ARGS__ }, \
71+
}
72+
73+
#define JH7100__INV(_idx, _name, _parent) [_idx] = { \
74+
.name = _name, \
75+
.flags = CLK_SET_RATE_PARENT, \
76+
.max = JH7100_CLK_INVERT, \
77+
.parents = { [0] = _parent }, \
78+
}
79+
80+
struct jh7100_clk {
81+
struct clk_hw hw;
82+
unsigned int idx;
83+
unsigned int max_div;
84+
};
85+
86+
struct jh7100_clk_priv {
87+
/* protect clk enable and set rate/parent from happening at the same time */
88+
spinlock_t rmw_lock;
89+
struct device *dev;
90+
void __iomem *base;
91+
struct clk_hw *pll[3];
92+
struct jh7100_clk reg[];
93+
};
94+
95+
const struct clk_ops *starfive_jh7100_clk_ops(u32 max);
96+
97+
#endif

0 commit comments

Comments
 (0)