drm/msm/a6xx: Introduce a6xx_llc_read

konradybcio · robclark · commit 26ed8d3dc06d · 2023-08-17T10:09:53.000-07:00
Add a helper that does exactly what it says on the can, it'll be required for A7xx. Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # sm8450 Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/551828/ Signed-off-by: Rob Clark <robdclark@chromium.org>
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -1740,6 +1740,11 @@ static void a6xx_llc_rmw(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 mask, u32 or)
 	return msm_rmw(a6xx_gpu->llc_mmio + (reg << 2), mask, or);
 }
 
+static u32 a6xx_llc_read(struct a6xx_gpu *a6xx_gpu, u32 reg)
+{
+	return msm_readl(a6xx_gpu->llc_mmio + (reg << 2));
+}
+
 static void a6xx_llc_write(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 value)
 {
 	msm_writel(value, a6xx_gpu->llc_mmio + (reg << 2));

Original file line number	Diff line number	Diff line change
`@@ -1740,6 +1740,11 @@ static void a6xx_llc_rmw(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 mask, u32 or)`
`1740`	`1740`	`return msm_rmw(a6xx_gpu->llc_mmio + (reg << 2), mask, or);`
`1741`	`1741`	`}`
`1742`	`1742`
	`1743`	`+static u32 a6xx_llc_read(struct a6xx_gpu *a6xx_gpu, u32 reg)`
	`1744`	`+{`
	`1745`	`+ return msm_readl(a6xx_gpu->llc_mmio + (reg << 2));`
	`1746`	`+}`
	`1747`	`+`
`1743`	`1748`	`static void a6xx_llc_write(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 value)`
`1744`	`1749`	`{`
`1745`	`1750`	`msm_writel(value, a6xx_gpu->llc_mmio + (reg << 2));`