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clk: mediatek: Add MT8188 apmixedsys clock support
Add MT8188 apmixedsys clock controller which provides Plls generated from SoC 26m and ssusb clock gate control. Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230331123621.16167-3-Garmin.Chang@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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‎drivers/clk/mediatek/Kconfig‎

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@@ -683,6 +683,15 @@ config COMMON_CLK_MT8186_VENCSYS
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help
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This driver supports MediaTek MT8186 vencsys clocks.
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config COMMON_CLK_MT8188
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tristate "Clock driver for MediaTek MT8188"
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depends on ARM64 || COMPILE_TEST
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select COMMON_CLK_MEDIATEK
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select COMMON_CLK_MEDIATEK_FHCTL
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default ARCH_MEDIATEK
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help
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This driver supports MediaTek MT8188 clocks.
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config COMMON_CLK_MT8192
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tristate "Clock driver for MediaTek MT8192"
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depends on ARM64 || COMPILE_TEST

‎drivers/clk/mediatek/Makefile‎

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@@ -100,6 +100,7 @@ obj-$(CONFIG_COMMON_CLK_MT8186_MMSYS) += clk-mt8186-mm.o
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obj-$(CONFIG_COMMON_CLK_MT8186_VDECSYS) += clk-mt8186-vdec.o
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obj-$(CONFIG_COMMON_CLK_MT8186_VENCSYS) += clk-mt8186-venc.o
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obj-$(CONFIG_COMMON_CLK_MT8186_WPESYS) += clk-mt8186-wpe.o
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obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o
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obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192-apmixedsys.o clk-mt8192.o
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obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
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obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o

‎drivers/clk/mediatek/clk-mt8188-apmixedsys.c‎

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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Garmin Chang <garmin.chang@mediatek.com>
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*/
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#include <dt-bindings/clock/mediatek,mt8188-clk.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include "clk-gate.h"
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#include "clk-mtk.h"
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#include "clk-pll.h"
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static const struct mtk_gate_regs apmixed_cg_regs = {
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.set_ofs = 0x8,
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.clr_ofs = 0x8,
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.sta_ofs = 0x8,
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};
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#define GATE_APMIXED(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &apmixed_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
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static const struct mtk_gate apmixed_clks[] = {
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GATE_APMIXED(CLK_APMIXED_PLL_SSUSB26M_EN, "pll_ssusb26m_en", "clk26m", 1),
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};
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#define MT8188_PLL_FMAX (3800UL * MHZ)
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#define MT8188_PLL_FMIN (1500UL * MHZ)
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#define MT8188_INTEGER_BITS 8
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#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
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_rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \
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_tuner_reg, _tuner_en_reg, _tuner_en_bit, \
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_pcw_reg, _pcw_shift, _pcw_chg_reg, \
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_en_reg, _pll_en_bit) { \
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.id = _id, \
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.name = _name, \
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.reg = _reg, \
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.pwr_reg = _pwr_reg, \
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.en_mask = _en_mask, \
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.flags = _flags, \
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.rst_bar_mask = _rst_bar_mask, \
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.fmax = MT8188_PLL_FMAX, \
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.fmin = MT8188_PLL_FMIN, \
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.pcwbits = _pcwbits, \
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.pcwibits = MT8188_INTEGER_BITS, \
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.pd_reg = _pd_reg, \
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.pd_shift = _pd_shift, \
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.tuner_reg = _tuner_reg, \
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.tuner_en_reg = _tuner_en_reg, \
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.tuner_en_bit = _tuner_en_bit, \
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.pcw_reg = _pcw_reg, \
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.pcw_shift = _pcw_shift, \
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.pcw_chg_reg = _pcw_chg_reg, \
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.en_reg = _en_reg, \
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.pll_en_bit = _pll_en_bit, \
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}
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static const struct mtk_pll_data plls[] = {
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PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x044C, 0x0458, 0,
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0, 0, 22, 0x0450, 24, 0, 0, 0, 0x0450, 0, 0, 0, 9),
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PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0514, 0x0520, 0,
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0, 0, 22, 0x0518, 24, 0, 0, 0, 0x0518, 0, 0, 0, 9),
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PLL(CLK_APMIXED_TVDPLL1, "tvdpll1", 0x0524, 0x0530, 0,
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0, 0, 22, 0x0528, 24, 0, 0, 0, 0x0528, 0, 0, 0, 9),
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PLL(CLK_APMIXED_TVDPLL2, "tvdpll2", 0x0534, 0x0540, 0,
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0, 0, 22, 0x0538, 24, 0, 0, 0, 0x0538, 0, 0, 0, 9),
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PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0544, 0x0550, 0xff000000,
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HAVE_RST_BAR, BIT(23), 22, 0x0548, 24, 0, 0, 0, 0x0548, 0, 0, 0, 9),
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PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x045C, 0x0468, 0xff000000,
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HAVE_RST_BAR, BIT(23), 22, 0x0460, 24, 0, 0, 0, 0x0460, 0, 0, 0, 9),
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PLL(CLK_APMIXED_IMGPLL, "imgpll", 0x0554, 0x0560, 0,
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0, 0, 22, 0x0558, 24, 0, 0, 0, 0x0558, 0, 0, 0, 9),
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PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0504, 0x0510, 0xff000000,
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HAVE_RST_BAR, BIT(23), 22, 0x0508, 24, 0, 0, 0, 0x0508, 0, 0, 0, 9),
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PLL(CLK_APMIXED_ADSPPLL, "adsppll", 0x042C, 0x0438, 0,
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0, 0, 22, 0x0430, 24, 0, 0, 0, 0x0430, 0, 0, 0, 9),
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PLL(CLK_APMIXED_APLL1, "apll1", 0x0304, 0x0314, 0,
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0, 0, 32, 0x0308, 24, 0x0034, 0x0000, 12, 0x030C, 0, 0, 0, 9),
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PLL(CLK_APMIXED_APLL2, "apll2", 0x0318, 0x0328, 0,
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0, 0, 32, 0x031C, 24, 0x0038, 0x0000, 13, 0x0320, 0, 0, 0, 9),
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PLL(CLK_APMIXED_APLL3, "apll3", 0x032C, 0x033C, 0,
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0, 0, 32, 0x0330, 24, 0x003C, 0x0000, 14, 0x0334, 0, 0, 0, 9),
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PLL(CLK_APMIXED_APLL4, "apll4", 0x0404, 0x0414, 0,
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0, 0, 32, 0x0408, 24, 0x0040, 0x0000, 15, 0x040C, 0, 0, 0, 9),
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PLL(CLK_APMIXED_APLL5, "apll5", 0x0418, 0x0428, 0,
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0, 0, 32, 0x041C, 24, 0x0044, 0x0000, 16, 0x0420, 0, 0, 0, 9),
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PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0340, 0x034C, 0,
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0, 0, 22, 0x0344, 24, 0, 0, 0, 0x0344, 0, 0, 0, 9),
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};
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static const struct of_device_id of_match_clk_mt8188_apmixed[] = {
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{ .compatible = "mediatek,mt8188-apmixedsys" },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, of_match_clk_mt8188_apmixed);
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static int clk_mt8188_apmixed_probe(struct platform_device *pdev)
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{
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struct clk_hw_onecell_data *clk_data;
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struct device_node *node = pdev->dev.of_node;
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int r;
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clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
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if (!clk_data)
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return -ENOMEM;
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r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
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if (r)
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goto free_apmixed_data;
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r = mtk_clk_register_gates(&pdev->dev, node, apmixed_clks,
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ARRAY_SIZE(apmixed_clks), clk_data);
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if (r)
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goto unregister_plls;
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r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
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if (r)
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goto unregister_gates;
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platform_set_drvdata(pdev, clk_data);
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return 0;
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unregister_gates:
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mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);
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unregister_plls:
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mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
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free_apmixed_data:
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mtk_free_clk_data(clk_data);
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return r;
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}
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static int clk_mt8188_apmixed_remove(struct platform_device *pdev)
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{
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struct device_node *node = pdev->dev.of_node;
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struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
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of_clk_del_provider(node);
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mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);
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mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
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mtk_free_clk_data(clk_data);
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return 0;
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}
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static struct platform_driver clk_mt8188_apmixed_drv = {
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.probe = clk_mt8188_apmixed_probe,
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.remove = clk_mt8188_apmixed_remove,
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.driver = {
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.name = "clk-mt8188-apmixed",
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.of_match_table = of_match_clk_mt8188_apmixed,
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},
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};
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module_platform_driver(clk_mt8188_apmixed_drv);
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MODULE_LICENSE("GPL");

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