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Commit 28e0377

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spi: mchp-pci1xxxx: Fix minor bugs in spi-pci1xxxx
Merge series from Tharun Kumar P <tharunkumar.pasumarthi@microchip.com>: This patch series fixes the following bugs in spi-pci1xxxx driver: 1. Length of SPI transactions is improper 2. SPI transactions fail after suspend and resume 3. Incorrect implementation of pci1xxxx_spi_set_cs API
2 parents 4084c8c + 45d2af8 commit 28e0377

1 file changed

Lines changed: 7 additions & 13 deletions

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drivers/spi/spi-pci1xxxx.c

Lines changed: 7 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -58,7 +58,7 @@
5858
#define VENDOR_ID_MCHP 0x1055
5959

6060
#define SPI_SUSPEND_CONFIG 0x101
61-
#define SPI_RESUME_CONFIG 0x303
61+
#define SPI_RESUME_CONFIG 0x203
6262

6363
struct pci1xxxx_spi_internal {
6464
u8 hw_inst;
@@ -114,17 +114,14 @@ static void pci1xxxx_spi_set_cs(struct spi_device *spi, bool enable)
114114

115115
/* Set the DEV_SEL bits of the SPI_MST_CTL_REG */
116116
regval = readl(par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst));
117-
if (enable) {
117+
if (!enable) {
118+
regval |= SPI_FORCE_CE;
118119
regval &= ~SPI_MST_CTL_DEVSEL_MASK;
119120
regval |= (spi_get_chipselect(spi, 0) << 25);
120-
writel(regval,
121-
par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst));
122121
} else {
123-
regval &= ~(spi_get_chipselect(spi, 0) << 25);
124-
writel(regval,
125-
par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst));
126-
122+
regval &= ~SPI_FORCE_CE;
127123
}
124+
writel(regval, par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst));
128125
}
129126

130127
static u8 pci1xxxx_get_clock_div(u32 hz)
@@ -199,8 +196,9 @@ static int pci1xxxx_spi_transfer_one(struct spi_controller *spi_ctlr,
199196
else
200197
regval &= ~SPI_MST_CTL_MODE_SEL;
201198

202-
regval |= ((clkdiv << 5) | SPI_FORCE_CE | (len << 8));
199+
regval |= (clkdiv << 5);
203200
regval &= ~SPI_MST_CTL_CMD_LEN_MASK;
201+
regval |= (len << 8);
204202
writel(regval, par->reg_base +
205203
SPI_MST_CTL_REG_OFFSET(p->hw_inst));
206204
regval = readl(par->reg_base +
@@ -222,10 +220,6 @@ static int pci1xxxx_spi_transfer_one(struct spi_controller *spi_ctlr,
222220
}
223221
}
224222
}
225-
226-
regval = readl(par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst));
227-
regval &= ~SPI_FORCE_CE;
228-
writel(regval, par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst));
229223
p->spi_xfer_in_progress = false;
230224

231225
return 0;

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