Skip to content

Commit 2afd1c2

Browse files
committed
Merge tag 'v5.14-rockchip-drivers1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/drivers
Yaml conversion of grf, pmu and power-domain bindings, Power-domains for rk3568 + necessary plumbing, Fixes for the usbphy bindings. * tag 'v5.14-rockchip-drivers1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: dt-bindings: soc: rockchip: drop unnecessary #phy-cells from grf.yaml dt-bindings: soc: rockchip: grf: add compatible for RK3308 USB grf dt-bindings: phy: rename phy nodename in phy-rockchip-inno-usb2.yaml dt-bindings: soc: rockchip: convert grf.txt to YAML soc: rockchip: power-domain: add rk3568 powerdomains dt-bindings: power: rockchip: Add bindings for RK3568 Soc dt-bindings: power: rockchip: Convert to json-schema dt-bindings: arm: rockchip: add more compatible strings to pmu.yaml dt-bindings: arm: rockchip: convert pmu.txt to YAML soc: rockchip: power-domain: Add a meaningful power domain name dt-bindings: add power-domain header for RK3568 SoCs Link: https://lore.kernel.org/r/4647955.GXAFRqVoOG@phil Signed-off-by: Olof Johansson <olof@lixom.net>
2 parents 1154842 + fcafd31 commit 2afd1c2

9 files changed

Lines changed: 744 additions & 328 deletions

File tree

Documentation/devicetree/bindings/arm/rockchip/pmu.txt

Lines changed: 0 additions & 16 deletions
This file was deleted.
Lines changed: 55 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,55 @@
1+
# SPDX-License-Identifier: GPL-2.0
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/arm/rockchip/pmu.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: Rockchip Power Management Unit (PMU)
8+
9+
maintainers:
10+
- Elaine Zhang <zhangqing@rock-chips.com>
11+
- Heiko Stuebner <heiko@sntech.de>
12+
13+
description: |
14+
The PMU is used to turn on and off different power domains of the SoCs.
15+
This includes the power to the CPU cores.
16+
17+
select:
18+
properties:
19+
compatible:
20+
contains:
21+
enum:
22+
- rockchip,px30-pmu
23+
- rockchip,rk3066-pmu
24+
- rockchip,rk3288-pmu
25+
- rockchip,rk3399-pmu
26+
27+
required:
28+
- compatible
29+
30+
properties:
31+
compatible:
32+
items:
33+
- enum:
34+
- rockchip,px30-pmu
35+
- rockchip,rk3066-pmu
36+
- rockchip,rk3288-pmu
37+
- rockchip,rk3399-pmu
38+
- const: syscon
39+
- const: simple-mfd
40+
41+
reg:
42+
maxItems: 1
43+
44+
required:
45+
- compatible
46+
- reg
47+
48+
additionalProperties: true
49+
50+
examples:
51+
- |
52+
pmu@20004000 {
53+
compatible = "rockchip,rk3066-pmu", "syscon", "simple-mfd";
54+
reg = <0x20004000 0x100>;
55+
};

Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml

Lines changed: 3 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -29,9 +29,6 @@ properties:
2929
"#clock-cells":
3030
const: 0
3131

32-
"#phy-cells":
33-
const: 0
34-
3532
clocks:
3633
maxItems: 1
3734

@@ -119,7 +116,6 @@ required:
119116
- reg
120117
- clock-output-names
121118
- "#clock-cells"
122-
- "#phy-cells"
123119
- host-port
124120
- otg-port
125121

@@ -130,26 +126,25 @@ examples:
130126
#include <dt-bindings/clock/rk3399-cru.h>
131127
#include <dt-bindings/interrupt-controller/arm-gic.h>
132128
#include <dt-bindings/interrupt-controller/irq.h>
133-
u2phy0: usb2-phy@e450 {
129+
u2phy0: usb2phy@e450 {
134130
compatible = "rockchip,rk3399-usb2phy";
135131
reg = <0xe450 0x10>;
136132
clocks = <&cru SCLK_USB2PHY0_REF>;
137133
clock-names = "phyclk";
138134
clock-output-names = "clk_usbphy0_480m";
139135
#clock-cells = <0>;
140-
#phy-cells = <0>;
141136
142137
u2phy0_host: host-port {
143-
#phy-cells = <0>;
144138
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
145139
interrupt-names = "linestate";
140+
#phy-cells = <0>;
146141
};
147142
148143
u2phy0_otg: otg-port {
149-
#phy-cells = <0>;
150144
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
151145
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
152146
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
153147
interrupt-names = "otg-bvalid", "otg-id", "linestate";
148+
#phy-cells = <0>;
154149
};
155150
};
Lines changed: 248 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,248 @@
1+
# SPDX-License-Identifier: GPL-2.0
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/power/rockchip,power-controller.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: Rockchip Power Domains
8+
9+
maintainers:
10+
- Elaine Zhang <zhangqing@rock-chips.com>
11+
- Heiko Stuebner <heiko@sntech.de>
12+
13+
description: |
14+
Rockchip processors include support for multiple power domains
15+
which can be powered up/down by software based on different
16+
application scenarios to save power.
17+
18+
Power domains contained within power-controller node are
19+
generic power domain providers documented in
20+
Documentation/devicetree/bindings/power/power-domain.yaml.
21+
22+
IP cores belonging to a power domain should contain a
23+
"power-domains" property that is a phandle for the
24+
power domain node representing the domain.
25+
26+
properties:
27+
$nodename:
28+
const: power-controller
29+
30+
compatible:
31+
enum:
32+
- rockchip,px30-power-controller
33+
- rockchip,rk3036-power-controller
34+
- rockchip,rk3066-power-controller
35+
- rockchip,rk3128-power-controller
36+
- rockchip,rk3188-power-controller
37+
- rockchip,rk3228-power-controller
38+
- rockchip,rk3288-power-controller
39+
- rockchip,rk3328-power-controller
40+
- rockchip,rk3366-power-controller
41+
- rockchip,rk3368-power-controller
42+
- rockchip,rk3399-power-controller
43+
- rockchip,rk3568-power-controller
44+
45+
"#power-domain-cells":
46+
const: 1
47+
48+
"#address-cells":
49+
const: 1
50+
51+
"#size-cells":
52+
const: 0
53+
54+
required:
55+
- compatible
56+
- "#power-domain-cells"
57+
58+
additionalProperties: false
59+
60+
patternProperties:
61+
"^power-domain@[0-9a-f]+$":
62+
63+
$ref: "#/$defs/pd-node"
64+
65+
unevaluatedProperties: false
66+
67+
properties:
68+
"#address-cells":
69+
const: 1
70+
71+
"#size-cells":
72+
const: 0
73+
74+
patternProperties:
75+
"^power-domain@[0-9a-f]+$":
76+
77+
$ref: "#/$defs/pd-node"
78+
79+
unevaluatedProperties: false
80+
81+
properties:
82+
"#address-cells":
83+
const: 1
84+
85+
"#size-cells":
86+
const: 0
87+
88+
patternProperties:
89+
"^power-domain@[0-9a-f]+$":
90+
91+
$ref: "#/$defs/pd-node"
92+
93+
unevaluatedProperties: false
94+
95+
properties:
96+
"#power-domain-cells":
97+
const: 0
98+
99+
$defs:
100+
pd-node:
101+
type: object
102+
description: |
103+
Represents the power domains within the power controller node.
104+
105+
properties:
106+
reg:
107+
maxItems: 1
108+
description: |
109+
Power domain index. Valid values are defined in
110+
"include/dt-bindings/power/px30-power.h"
111+
"include/dt-bindings/power/rk3036-power.h"
112+
"include/dt-bindings/power/rk3066-power.h"
113+
"include/dt-bindings/power/rk3128-power.h"
114+
"include/dt-bindings/power/rk3188-power.h"
115+
"include/dt-bindings/power/rk3228-power.h"
116+
"include/dt-bindings/power/rk3288-power.h"
117+
"include/dt-bindings/power/rk3328-power.h"
118+
"include/dt-bindings/power/rk3366-power.h"
119+
"include/dt-bindings/power/rk3368-power.h"
120+
"include/dt-bindings/power/rk3399-power.h"
121+
"include/dt-bindings/power/rk3568-power.h"
122+
123+
clocks:
124+
minItems: 1
125+
maxItems: 30
126+
description: |
127+
A number of phandles to clocks that need to be enabled
128+
while power domain switches state.
129+
130+
pm_qos:
131+
$ref: /schemas/types.yaml#/definitions/phandle-array
132+
description: |
133+
A number of phandles to qos blocks which need to be saved and restored
134+
while power domain switches state.
135+
136+
"#power-domain-cells":
137+
enum: [0, 1]
138+
description:
139+
Must be 0 for nodes representing a single PM domain and 1 for nodes
140+
providing multiple PM domains.
141+
142+
required:
143+
- reg
144+
- "#power-domain-cells"
145+
146+
examples:
147+
- |
148+
#include <dt-bindings/clock/rk3399-cru.h>
149+
#include <dt-bindings/power/rk3399-power.h>
150+
151+
soc {
152+
#address-cells = <2>;
153+
#size-cells = <2>;
154+
155+
qos_hdcp: qos@ffa90000 {
156+
compatible = "rockchip,rk3399-qos", "syscon";
157+
reg = <0x0 0xffa90000 0x0 0x20>;
158+
};
159+
160+
qos_iep: qos@ffa98000 {
161+
compatible = "rockchip,rk3399-qos", "syscon";
162+
reg = <0x0 0xffa98000 0x0 0x20>;
163+
};
164+
165+
qos_rga_r: qos@ffab0000 {
166+
compatible = "rockchip,rk3399-qos", "syscon";
167+
reg = <0x0 0xffab0000 0x0 0x20>;
168+
};
169+
170+
qos_rga_w: qos@ffab0080 {
171+
compatible = "rockchip,rk3399-qos", "syscon";
172+
reg = <0x0 0xffab0080 0x0 0x20>;
173+
};
174+
175+
qos_video_m0: qos@ffab8000 {
176+
compatible = "rockchip,rk3399-qos", "syscon";
177+
reg = <0x0 0xffab8000 0x0 0x20>;
178+
};
179+
180+
qos_video_m1_r: qos@ffac0000 {
181+
compatible = "rockchip,rk3399-qos", "syscon";
182+
reg = <0x0 0xffac0000 0x0 0x20>;
183+
};
184+
185+
qos_video_m1_w: qos@ffac0080 {
186+
compatible = "rockchip,rk3399-qos", "syscon";
187+
reg = <0x0 0xffac0080 0x0 0x20>;
188+
};
189+
190+
power-management@ff310000 {
191+
compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
192+
reg = <0x0 0xff310000 0x0 0x1000>;
193+
194+
power-controller {
195+
compatible = "rockchip,rk3399-power-controller";
196+
#power-domain-cells = <1>;
197+
#address-cells = <1>;
198+
#size-cells = <0>;
199+
200+
/* These power domains are grouped by VD_CENTER */
201+
power-domain@RK3399_PD_IEP {
202+
reg = <RK3399_PD_IEP>;
203+
clocks = <&cru ACLK_IEP>,
204+
<&cru HCLK_IEP>;
205+
pm_qos = <&qos_iep>;
206+
#power-domain-cells = <0>;
207+
};
208+
power-domain@RK3399_PD_RGA {
209+
reg = <RK3399_PD_RGA>;
210+
clocks = <&cru ACLK_RGA>,
211+
<&cru HCLK_RGA>;
212+
pm_qos = <&qos_rga_r>,
213+
<&qos_rga_w>;
214+
#power-domain-cells = <0>;
215+
};
216+
power-domain@RK3399_PD_VCODEC {
217+
reg = <RK3399_PD_VCODEC>;
218+
clocks = <&cru ACLK_VCODEC>,
219+
<&cru HCLK_VCODEC>;
220+
pm_qos = <&qos_video_m0>;
221+
#power-domain-cells = <0>;
222+
};
223+
power-domain@RK3399_PD_VDU {
224+
reg = <RK3399_PD_VDU>;
225+
clocks = <&cru ACLK_VDU>,
226+
<&cru HCLK_VDU>;
227+
pm_qos = <&qos_video_m1_r>,
228+
<&qos_video_m1_w>;
229+
#power-domain-cells = <0>;
230+
};
231+
power-domain@RK3399_PD_VIO {
232+
reg = <RK3399_PD_VIO>;
233+
#power-domain-cells = <1>;
234+
#address-cells = <1>;
235+
#size-cells = <0>;
236+
237+
power-domain@RK3399_PD_HDCP {
238+
reg = <RK3399_PD_HDCP>;
239+
clocks = <&cru ACLK_HDCP>,
240+
<&cru HCLK_HDCP>,
241+
<&cru PCLK_HDCP>;
242+
pm_qos = <&qos_hdcp>;
243+
#power-domain-cells = <0>;
244+
};
245+
};
246+
};
247+
};
248+
};

0 commit comments

Comments
 (0)