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Merge tag 'tenstorrent-dt-for-v6.19' of https://github.com/tenstorrent/linux into soc/newsoc
Tenstorrent device tree for v6.19 Add Tenstorrent as a vendor and enable support for the Blackhole SoC in Blackhole P100 and P150 PCIe cards. The SoC contains four RISC-V CPU tiles consisting of 4x SiFive X280 cores. There is a virtual UART implemented in OpenSBI firmware that allows a console program on the PCIe host to communicate through shared memory with Linux running on the Blackhole card. Link: https://github.com/tenstorrent/tt-bh-linux Link: https://github.com/tenstorrent/opensbi/ Signed-off-by: Drew Fustini <fustini@kernel.org> * tag 'tenstorrent-dt-for-v6.19' of https://github.com/tenstorrent/linux: riscv: defconfig: Enable Tenstorrent SoCs riscv: Kconfig.socs: Add ARCH_TENSTORRENT for Tenstorrent SoCs riscv: dts: Add Tenstorrent Blackhole SoC PCIe cards dt-bindings: interrupt-controller: Add Tenstorrent Blackhole compatible dt-bindings: timers: Add Tenstorrent Blackhole compatible dt-bindings: riscv: cpus: Add SiFive X280 compatible dt-bindings: riscv: Add Tenstorrent Blackhole compatible dt-bindings: vendor-prefixes: Add Tenstorrent AI ULC
2 parents dcb6fa3 + a71e6e8 commit 2bab992

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Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml

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- spacemit,k1-plic
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- starfive,jh7100-plic
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- starfive,jh7110-plic
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- tenstorrent,blackhole-plic
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- const: sifive,plic-1.0.0
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- items:
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- enum:

Documentation/devicetree/bindings/riscv/cpus.yaml

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- enum:
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- sifive,e51
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- sifive,u54-mc
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- sifive,x280
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- const: sifive,rocket0
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- const: riscv
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- const: riscv # Simulator only
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/riscv/tenstorrent.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Tenstorrent SoC-based boards
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maintainers:
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- Drew Fustini <dfustini@oss.tenstorrent.com>
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- Joel Stanley <jms@oss.tenstorrent.com>
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description:
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Tenstorrent SoC-based boards
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properties:
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$nodename:
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const: '/'
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compatible:
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oneOf:
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- description: Tenstorrent Blackhole PCIe card
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items:
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- const: tenstorrent,blackhole-card
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- const: tenstorrent,blackhole
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additionalProperties: true
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...

Documentation/devicetree/bindings/timer/sifive,clint.yaml

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- starfive,jh7100-clint # StarFive JH7100
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- starfive,jh7110-clint # StarFive JH7110
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- starfive,jh8100-clint # StarFive JH8100
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- tenstorrent,blackhole-clint # Tenstorrent Blackhole
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- const: sifive,clint0 # SiFive CLINT v0 IP block
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- items:
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- {}

Documentation/devicetree/bindings/vendor-prefixes.yaml

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description: Tempo Semiconductor
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"^tenda,.*":
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description: Shenzhen Tenda Technology Co., Ltd.
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"^tenstorrent,.*":
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description: Tenstorrent AI ULC
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"^terasic,.*":
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description: Terasic Inc.
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"^tesla,.*":

MAINTAINERS

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N: spacemit
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K: spacemit
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RISC-V TENSTORRENT SoC SUPPORT
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M: Drew Fustini <dfustini@oss.tenstorrent.com>
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M: Joel Stanley <jms@oss.tenstorrent.com>
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L: linux-riscv@lists.infradead.org
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S: Maintained
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T: git https://github.com/tenstorrent/linux.git
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F: Documentation/devicetree/bindings/riscv/tenstorrent.yaml
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F: arch/riscv/boot/dts/tenstorrent/
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RISC-V THEAD SoC SUPPORT
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M: Drew Fustini <fustini@kernel.org>
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M: Guo Ren <guoren@kernel.org>

arch/riscv/Kconfig.socs

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This enables support for Allwinner sun20i platform hardware,
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including boards based on the D1 and D1s SoCs.
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config ARCH_TENSTORRENT
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bool "Tenstorrent SoCs"
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help
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This enables support for Tenstorrent SoC platforms.
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Current support is for Blackhole P100 and P150 PCIe cards.
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The Blackhole SoC contains four RISC-V CPU tiles each
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consisting of 4x SiFive X280 cores.
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config ARCH_THEAD
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bool "T-HEAD RISC-V SoCs"
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depends on MMU && !XIP_KERNEL

arch/riscv/boot/dts/Makefile

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subdir-y += sophgo
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subdir-y += spacemit
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subdir-y += starfive
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subdir-y += tenstorrent
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subdir-y += thead
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# SPDX-License-Identifier: GPL-2.0
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dtb-$(CONFIG_ARCH_TENSTORRENT) += blackhole-card.dtb
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/dts-v1/;
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#include "blackhole.dtsi"
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/ {
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model = "Tenstorrent Blackhole";
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compatible = "tenstorrent,blackhole-card", "tenstorrent,blackhole";
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memory@400030000000 {
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device_type = "memory";
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reg = <0x4000 0x30000000 0x1 0x00000000>;
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};
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};

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