@@ -65,7 +65,9 @@ Required properties:
6565
6666- OPP nodes: One or more OPP nodes describing voltage-current-frequency
6767 combinations. Their name isn't significant but their phandle can be used to
68- reference an OPP.
68+ reference an OPP. These are mandatory except for the case where the OPP table
69+ is present only to indicate dependency between devices using the opp-shared
70+ property.
6971
7072Optional properties:
7173- opp-shared: Indicates that device nodes using this OPP Table Node's phandle
@@ -568,3 +570,53 @@ Example 6: opp-microvolt-<name>, opp-microamp-<name>:
568570 };
569571 };
570572};
573+
574+ Example 7: Single cluster Quad-core ARM cortex A53, OPP points from firmware,
575+ distinct clock controls but two sets of clock/voltage/current lines.
576+
577+ / {
578+ cpus {
579+ #address-cells = <2>;
580+ #size-cells = <0>;
581+
582+ cpu@0 {
583+ compatible = "arm,cortex-a53";
584+ reg = <0x0 0x100>;
585+ next-level-cache = <&A53_L2>;
586+ clocks = <&dvfs_controller 0>;
587+ operating-points-v2 = <&cpu_opp0_table>;
588+ };
589+ cpu@1 {
590+ compatible = "arm,cortex-a53";
591+ reg = <0x0 0x101>;
592+ next-level-cache = <&A53_L2>;
593+ clocks = <&dvfs_controller 1>;
594+ operating-points-v2 = <&cpu_opp0_table>;
595+ };
596+ cpu@2 {
597+ compatible = "arm,cortex-a53";
598+ reg = <0x0 0x102>;
599+ next-level-cache = <&A53_L2>;
600+ clocks = <&dvfs_controller 2>;
601+ operating-points-v2 = <&cpu_opp1_table>;
602+ };
603+ cpu@3 {
604+ compatible = "arm,cortex-a53";
605+ reg = <0x0 0x103>;
606+ next-level-cache = <&A53_L2>;
607+ clocks = <&dvfs_controller 3>;
608+ operating-points-v2 = <&cpu_opp1_table>;
609+ };
610+
611+ };
612+
613+ cpu_opp0_table: opp0_table {
614+ compatible = "operating-points-v2";
615+ opp-shared;
616+ };
617+
618+ cpu_opp1_table: opp1_table {
619+ compatible = "operating-points-v2";
620+ opp-shared;
621+ };
622+ };
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