Skip to content

Commit 2cc6710

Browse files
brooniebroonie
committed
MediaTek devicetree/bindings warnings sanitization
Merge series from Julien Massot <julien.massot@collabora.com>: This patch series continues the effort to address Device Tree validation warnings for MediaTek platforms, with a focus on MT8183. It follows the initial cleanup series by Angelo (https://www.spinics.net/lists/kernel/msg5780177.html). The patches in this set eliminate several of the remaining warnings by improving or converting DT bindings to DT schema, adding missing properties, and updating device tree files accordingly.
2 parents 6be9886 + 82fd5dc commit 2cc6710

6 files changed

Lines changed: 336 additions & 88 deletions

File tree

‎Documentation/devicetree/bindings/sound/mediatek,mt8183-audio.yaml‎

Lines changed: 228 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,228 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/sound/mediatek,mt8183-audio.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: Mediatek AFE PCM controller for mt8183
8+
9+
maintainers:
10+
- Julien Massot <jmassot@collabora.com>
11+
12+
properties:
13+
compatible:
14+
const: mediatek,mt8183-audio
15+
16+
interrupts:
17+
maxItems: 1
18+
19+
resets:
20+
maxItems: 1
21+
22+
reset-names:
23+
const: audiosys
24+
25+
power-domains:
26+
maxItems: 1
27+
28+
memory-region:
29+
maxItems: 1
30+
31+
clocks:
32+
items:
33+
- description: AFE clock
34+
- description: ADDA DAC clock
35+
- description: ADDA DAC pre-distortion clock
36+
- description: ADDA ADC clock
37+
- description: ADDA6 ADC clock
38+
- description: Audio low-jitter 22.5792m clock
39+
- description: Audio low-jitter 24.576m clock
40+
- description: Audio PLL1 tuner clock
41+
- description: Audio PLL2 tuner clock
42+
- description: I2S1 bit clock
43+
- description: I2S2 bit clock
44+
- description: I2S3 bit clock
45+
- description: I2S4 bit clock
46+
- description: Audio Time-Division Multiplexing interface clock
47+
- description: Powerdown Audio test model clock
48+
- description: Audio infra sys clock
49+
- description: Audio infra 26M clock
50+
- description: Mux for audio clock
51+
- description: Mux for audio internal bus clock
52+
- description: Mux main divider by 4
53+
- description: Primary audio mux
54+
- description: Primary audio PLL
55+
- description: Secondary audio mux
56+
- description: Secondary audio PLL
57+
- description: Primary audio en-generator clock
58+
- description: Primary PLL divider by 4 for IEC
59+
- description: Secondary audio en-generator clock
60+
- description: Secondary PLL divider by 8 for IEC
61+
- description: Mux selector for I2S port 0
62+
- description: Mux selector for I2S port 1
63+
- description: Mux selector for I2S port 2
64+
- description: Mux selector for I2S port 3
65+
- description: Mux selector for I2S port 4
66+
- description: Mux selector for I2S port 5
67+
- description: APLL1 and APLL2 divider for I2S port 0
68+
- description: APLL1 and APLL2 divider for I2S port 1
69+
- description: APLL1 and APLL2 divider for I2S port 2
70+
- description: APLL1 and APLL2 divider for I2S port 3
71+
- description: APLL1 and APLL2 divider for I2S port 4
72+
- description: APLL1 and APLL2 divider for IEC
73+
- description: 26MHz clock for audio subsystem
74+
75+
clock-names:
76+
items:
77+
- const: aud_afe_clk
78+
- const: aud_dac_clk
79+
- const: aud_dac_predis_clk
80+
- const: aud_adc_clk
81+
- const: aud_adc_adda6_clk
82+
- const: aud_apll22m_clk
83+
- const: aud_apll24m_clk
84+
- const: aud_apll1_tuner_clk
85+
- const: aud_apll2_tuner_clk
86+
- const: aud_i2s1_bclk_sw
87+
- const: aud_i2s2_bclk_sw
88+
- const: aud_i2s3_bclk_sw
89+
- const: aud_i2s4_bclk_sw
90+
- const: aud_tdm_clk
91+
- const: aud_tml_clk
92+
- const: aud_infra_clk
93+
- const: mtkaif_26m_clk
94+
- const: top_mux_audio
95+
- const: top_mux_aud_intbus
96+
- const: top_syspll_d2_d4
97+
- const: top_mux_aud_1
98+
- const: top_apll1_ck
99+
- const: top_mux_aud_2
100+
- const: top_apll2_ck
101+
- const: top_mux_aud_eng1
102+
- const: top_apll1_d8
103+
- const: top_mux_aud_eng2
104+
- const: top_apll2_d8
105+
- const: top_i2s0_m_sel
106+
- const: top_i2s1_m_sel
107+
- const: top_i2s2_m_sel
108+
- const: top_i2s3_m_sel
109+
- const: top_i2s4_m_sel
110+
- const: top_i2s5_m_sel
111+
- const: top_apll12_div0
112+
- const: top_apll12_div1
113+
- const: top_apll12_div2
114+
- const: top_apll12_div3
115+
- const: top_apll12_div4
116+
- const: top_apll12_divb
117+
- const: top_clk26m_clk
118+
119+
required:
120+
- compatible
121+
- interrupts
122+
- resets
123+
- reset-names
124+
- power-domains
125+
- clocks
126+
- clock-names
127+
128+
additionalProperties: false
129+
130+
examples:
131+
- |
132+
#include <dt-bindings/clock/mt8183-clk.h>
133+
#include <dt-bindings/interrupt-controller/arm-gic.h>
134+
#include <dt-bindings/interrupt-controller/irq.h>
135+
#include <dt-bindings/power/mt8183-power.h>
136+
#include <dt-bindings/reset/mt8183-resets.h>
137+
138+
audio-controller {
139+
compatible = "mediatek,mt8183-audio";
140+
interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>;
141+
resets = <&watchdog MT8183_TOPRGU_AUDIO_SW_RST>;
142+
reset-names = "audiosys";
143+
power-domains = <&spm MT8183_POWER_DOMAIN_AUDIO>;
144+
clocks = <&audiosys CLK_AUDIO_AFE>,
145+
<&audiosys CLK_AUDIO_DAC>,
146+
<&audiosys CLK_AUDIO_DAC_PREDIS>,
147+
<&audiosys CLK_AUDIO_ADC>,
148+
<&audiosys CLK_AUDIO_PDN_ADDA6_ADC>,
149+
<&audiosys CLK_AUDIO_22M>,
150+
<&audiosys CLK_AUDIO_24M>,
151+
<&audiosys CLK_AUDIO_APLL_TUNER>,
152+
<&audiosys CLK_AUDIO_APLL2_TUNER>,
153+
<&audiosys CLK_AUDIO_I2S1>,
154+
<&audiosys CLK_AUDIO_I2S2>,
155+
<&audiosys CLK_AUDIO_I2S3>,
156+
<&audiosys CLK_AUDIO_I2S4>,
157+
<&audiosys CLK_AUDIO_TDM>,
158+
<&audiosys CLK_AUDIO_TML>,
159+
<&infracfg CLK_INFRA_AUDIO>,
160+
<&infracfg CLK_INFRA_AUDIO_26M_BCLK>,
161+
<&topckgen CLK_TOP_MUX_AUDIO>,
162+
<&topckgen CLK_TOP_MUX_AUD_INTBUS>,
163+
<&topckgen CLK_TOP_SYSPLL_D2_D4>,
164+
<&topckgen CLK_TOP_MUX_AUD_1>,
165+
<&topckgen CLK_TOP_APLL1_CK>,
166+
<&topckgen CLK_TOP_MUX_AUD_2>,
167+
<&topckgen CLK_TOP_APLL2_CK>,
168+
<&topckgen CLK_TOP_MUX_AUD_ENG1>,
169+
<&topckgen CLK_TOP_APLL1_D8>,
170+
<&topckgen CLK_TOP_MUX_AUD_ENG2>,
171+
<&topckgen CLK_TOP_APLL2_D8>,
172+
<&topckgen CLK_TOP_MUX_APLL_I2S0>,
173+
<&topckgen CLK_TOP_MUX_APLL_I2S1>,
174+
<&topckgen CLK_TOP_MUX_APLL_I2S2>,
175+
<&topckgen CLK_TOP_MUX_APLL_I2S3>,
176+
<&topckgen CLK_TOP_MUX_APLL_I2S4>,
177+
<&topckgen CLK_TOP_MUX_APLL_I2S5>,
178+
<&topckgen CLK_TOP_APLL12_DIV0>,
179+
<&topckgen CLK_TOP_APLL12_DIV1>,
180+
<&topckgen CLK_TOP_APLL12_DIV2>,
181+
<&topckgen CLK_TOP_APLL12_DIV3>,
182+
<&topckgen CLK_TOP_APLL12_DIV4>,
183+
<&topckgen CLK_TOP_APLL12_DIVB>,
184+
<&clk26m>;
185+
clock-names = "aud_afe_clk",
186+
"aud_dac_clk",
187+
"aud_dac_predis_clk",
188+
"aud_adc_clk",
189+
"aud_adc_adda6_clk",
190+
"aud_apll22m_clk",
191+
"aud_apll24m_clk",
192+
"aud_apll1_tuner_clk",
193+
"aud_apll2_tuner_clk",
194+
"aud_i2s1_bclk_sw",
195+
"aud_i2s2_bclk_sw",
196+
"aud_i2s3_bclk_sw",
197+
"aud_i2s4_bclk_sw",
198+
"aud_tdm_clk",
199+
"aud_tml_clk",
200+
"aud_infra_clk",
201+
"mtkaif_26m_clk",
202+
"top_mux_audio",
203+
"top_mux_aud_intbus",
204+
"top_syspll_d2_d4",
205+
"top_mux_aud_1",
206+
"top_apll1_ck",
207+
"top_mux_aud_2",
208+
"top_apll2_ck",
209+
"top_mux_aud_eng1",
210+
"top_apll1_d8",
211+
"top_mux_aud_eng2",
212+
"top_apll2_d8",
213+
"top_i2s0_m_sel",
214+
"top_i2s1_m_sel",
215+
"top_i2s2_m_sel",
216+
"top_i2s3_m_sel",
217+
"top_i2s4_m_sel",
218+
"top_i2s5_m_sel",
219+
"top_apll12_div0",
220+
"top_apll12_div1",
221+
"top_apll12_div2",
222+
"top_apll12_div3",
223+
"top_apll12_div4",
224+
"top_apll12_divb",
225+
"top_clk26m_clk";
226+
};
227+
228+
...

‎Documentation/devicetree/bindings/sound/mediatek,mt8183_da7219.yaml‎

Lines changed: 49 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,49 @@
1+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/sound/mediatek,mt8183_da7219.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: MediaTek MT8183 sound card with external codecs
8+
9+
maintainers:
10+
- Julien Massot <jmassot@collabora.com>
11+
12+
description:
13+
MediaTek MT8183 SoC-based sound cards with DA7219 as headset codec,
14+
and MAX98357A, RT1015 or RT1015P as speaker amplifiers. Optionally includes HDMI codec.
15+
16+
properties:
17+
compatible:
18+
enum:
19+
- mediatek,mt8183_da7219_max98357
20+
- mediatek,mt8183_da7219_rt1015
21+
- mediatek,mt8183_da7219_rt1015p
22+
23+
mediatek,headset-codec:
24+
$ref: /schemas/types.yaml#/definitions/phandle
25+
description: Phandle to the DA7219 headset codec.
26+
27+
mediatek,platform:
28+
$ref: /schemas/types.yaml#/definitions/phandle
29+
description: Phandle to the MT8183 ASoC platform (e.g., AFE node).
30+
31+
mediatek,hdmi-codec:
32+
$ref: /schemas/types.yaml#/definitions/phandle
33+
description: Optional phandle to the HDMI codec (e.g., IT6505).
34+
35+
required:
36+
- compatible
37+
- mediatek,headset-codec
38+
- mediatek,platform
39+
40+
additionalProperties: false
41+
42+
examples:
43+
- |
44+
sound {
45+
compatible = "mediatek,mt8183_da7219_max98357";
46+
mediatek,headset-codec = <&da7219>;
47+
mediatek,hdmi-codec = <&it6505dptx>;
48+
mediatek,platform = <&afe>;
49+
};

‎Documentation/devicetree/bindings/sound/mediatek,mt8183_mt6358_ts3a227.yaml‎

Lines changed: 59 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,59 @@
1+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/sound/mediatek,mt8183_mt6358_ts3a227.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: MediaTek MT8183 sound card with MT6358, TS3A227, and MAX98357/RT1015 codecs
8+
9+
maintainers:
10+
- Julien Massot <julien.massot@collabora.com>
11+
12+
description:
13+
MediaTek MT8183 SoC-based sound cards using the MT6358 codec,
14+
with optional TS3A227 headset codec, EC codec (via Chrome EC), and HDMI audio.
15+
Speaker amplifier can be one of MAX98357A/B, RT1015, or RT1015P.
16+
17+
properties:
18+
compatible:
19+
enum:
20+
- mediatek,mt8183_mt6358_ts3a227_max98357
21+
- mediatek,mt8183_mt6358_ts3a227_max98357b
22+
- mediatek,mt8183_mt6358_ts3a227_rt1015
23+
- mediatek,mt8183_mt6358_ts3a227_rt1015p
24+
25+
mediatek,platform:
26+
$ref: /schemas/types.yaml#/definitions/phandle
27+
description: Phandle to the MT8183 ASoC platform node (e.g., AFE).
28+
29+
mediatek,headset-codec:
30+
$ref: /schemas/types.yaml#/definitions/phandle
31+
description: Phandle to the TS3A227 headset codec.
32+
33+
mediatek,ec-codec:
34+
$ref: /schemas/types.yaml#/definitions/phandle
35+
description: |
36+
Optional phandle to a ChromeOS EC codec node.
37+
See bindings in google,cros-ec-codec.yaml.
38+
39+
mediatek,hdmi-codec:
40+
$ref: /schemas/types.yaml#/definitions/phandle
41+
description: Optional phandle to an HDMI audio codec node.
42+
43+
required:
44+
- compatible
45+
- mediatek,platform
46+
47+
additionalProperties: false
48+
49+
examples:
50+
- |
51+
sound {
52+
compatible = "mediatek,mt8183_mt6358_ts3a227_max98357";
53+
mediatek,headset-codec = <&ts3a227>;
54+
mediatek,ec-codec = <&ec_codec>;
55+
mediatek,hdmi-codec = <&it6505dptx>;
56+
mediatek,platform = <&afe>;
57+
};
58+
59+
...

‎Documentation/devicetree/bindings/sound/mt8183-afe-pcm.txt‎

Lines changed: 0 additions & 42 deletions
This file was deleted.

0 commit comments

Comments
 (0)