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Merge tag 'imx-dt-6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt
i.MX ARM device tree changes for 6.7: - New board support: Variscite VAR-SOM-MX6 SoM and Custom board. - A bunch of dt-schema check fixes from Fabio Estevam. - A couple of MBA6ULX changes from Alexander Stein that marks gpio-buttons as wakeup-source and improves gpio-keys button node names. - Add ATM0700D4 panel support for sk-imx53 board. - Correct regulator node name for imx6qdl-nitrogen6 board. - A couple of Gateworks i.MX6QDL board update: adding MDIO nodes and populating Ethernet MAC address. * tag 'imx-dt-6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (31 commits) ARM: dts: imx7d-pico-pi: Disable USDHC1 ARM: dts: imx28: Fix dcp compatible ARM: dts: imx7s: Remove #power-domain-cells from gpcv2 ARM: dts: imx25: Remove clock-names from the watchdog ARM: dts: imx25: Fix sram node ARM: dts: imx25: Fix dryice node ARM: dts: imx6qdl-gw5904: add dt props for populating eth MAC addrs ARM: dts: vfxxx: Write dmas in a single line ARM: dts: imx27-phytec: Use eeprom as the node name ARM: dts: imx51: Remove invalid sahara compatible ARM: dts: imx53: Adjust the ecspi compatible ARM: dts: imx7ulp: Fix usbphy1 compatible ARM: dts: imx6q-pistachio: Use a valid value for fsl,tx-d-cal ARM: dts: imx6q-b650v3: Fix fsl,tx-cal-45-dn-ohms ARM: dts: imx28-tx28: Move phy_type to USB node ARM: dts: mxs: Switch to #pwm-cells = <3> ARM: dts: imx6q: Add Variscite MX6 Custom board support ARM: dts: imx6qdl: Add Variscite VAR-SOM-MX6 SoM support ARM: dts: mxs: Fix duart clock-names ARM: dts: imx6ull/7d-colibri: Fix compatible ... Link: https://lore.kernel.org/r/20231015132300.2268016-2-shawnguo@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2 parents 6a4347f + 46da7fd commit 2de3561

55 files changed

Lines changed: 1185 additions & 95 deletions

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arch/arm/boot/dts/nxp/imx/Makefile

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Original file line numberDiff line numberDiff line change
@@ -47,6 +47,8 @@ dtb-$(CONFIG_SOC_IMX53) += \
4747
imx53-qsb.dtb \
4848
imx53-qsrb.dtb \
4949
imx53-sk-imx53.dtb \
50+
imx53-sk-imx53-atm0700d4-lvds.dtb \
51+
imx53-sk-imx53-atm0700d4-rgb.dtb \
5052
imx53-smd.dtb \
5153
imx53-tx53-x03x.dtb \
5254
imx53-tx53-x13x.dtb \
@@ -244,6 +246,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
244246
imx6q-udoo.dtb \
245247
imx6q-utilite-pro.dtb \
246248
imx6q-var-dt6customboard.dtb \
249+
imx6q-var-mx6customboard.dtb \
247250
imx6q-vicut1.dtb \
248251
imx6q-wandboard.dtb \
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imx6q-wandboard-revb1.dtb \

arch/arm/boot/dts/nxp/imx/imx25.dtsi

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@@ -529,7 +529,6 @@
529529
compatible = "fsl,imx25-wdt", "fsl,imx21-wdt";
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reg = <0x53fdc000 0x4000>;
531531
clocks = <&clks 126>;
532-
clock-names = "";
533532
interrupts = <55>;
534533
};
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@@ -583,17 +582,19 @@
583582
};
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585584
dryice@53ffc000 {
586-
compatible = "fsl,imx25-dryice", "fsl,imx25-rtc";
585+
compatible = "fsl,imx25-rtc";
587586
reg = <0x53ffc000 0x4000>;
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clocks = <&clks 81>;
589-
clock-names = "ipg";
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interrupts = <25 56>;
591589
};
592590
};
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594592
iram: sram@78000000 {
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compatible = "mmio-sram";
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reg = <0x78000000 0x20000>;
595+
ranges = <0 0x78000000 0x20000>;
596+
#address-cells = <1>;
597+
#size-cells = <1>;
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};
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599600
emi@80000000 {

arch/arm/boot/dts/nxp/imx/imx27-phytec-phycard-s-som.dtsi

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@@ -34,7 +34,7 @@
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "okay";
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37-
at24@52 {
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eeprom@52 {
3838
compatible = "atmel,24c32";
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pagesize = <32>;
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reg = <0x52>;

arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-som.dtsi

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@@ -180,7 +180,7 @@
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "okay";
182182

183-
at24@52 {
183+
eeprom@52 {
184184
compatible = "atmel,24c32";
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pagesize = <32>;
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reg = <0x52>;

arch/arm/boot/dts/nxp/imx/imx51-zii-rdu1.dts

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@@ -119,8 +119,8 @@
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compatible = "i2c-gpio";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_swi2c>;
122-
gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>, /* sda */
123-
<&gpio3 4 GPIO_ACTIVE_HIGH>; /* scl */
122+
sda-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
123+
scl-gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
124124
i2c-gpio,delay-us = <50>;
125125
status = "okay";
126126

arch/arm/boot/dts/nxp/imx/imx51.dtsi

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@@ -651,7 +651,7 @@
651651
};
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sahara: crypto@83ff8000 {
654-
compatible = "fsl,imx53-sahara", "fsl,imx51-sahara";
654+
compatible = "fsl,imx53-sahara";
655655
reg = <0x83ff8000 0x4000>;
656656
interrupts = <19 20>;
657657
clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>,
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@@ -0,0 +1,97 @@
1+
// SPDX-License-Identifier: GPL-2.0+
2+
//
3+
// Copyright 2023 Linaro Ltd.
4+
5+
/dts-v1/;
6+
7+
#include <dt-bindings/pwm/pwm.h>
8+
#include "imx53-sk-imx53-atm0700d4.dtsi"
9+
10+
/ {
11+
lvds-decoder {
12+
compatible = "ti,sn65lvds94", "lvds-decoder";
13+
14+
ports {
15+
#address-cells = <1>;
16+
#size-cells = <0>;
17+
18+
port@0 {
19+
reg = <0>;
20+
21+
lvds_decoder_in: endpoint {
22+
remote-endpoint = <&lvds0_out>;
23+
};
24+
};
25+
26+
port@1 {
27+
reg = <1>;
28+
29+
lvds_decoder_out: endpoint {
30+
remote-endpoint = <&panel_rgb_in>;
31+
};
32+
};
33+
};
34+
};
35+
};
36+
37+
&iomuxc {
38+
pinctrl_lvds0: lvds0grp {
39+
/* LVDS pins only have pin mux configuration */
40+
fsl,pins = <
41+
MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000
42+
MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000
43+
MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000
44+
MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000
45+
MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000
46+
>;
47+
};
48+
49+
pinctrl_spi_gpio: spigrp {
50+
fsl,pins = <
51+
MX53_PAD_EIM_A22__GPIO2_16 0x1f4
52+
MX53_PAD_EIM_A21__GPIO2_17 0x1f4
53+
MX53_PAD_EIM_A16__GPIO2_22 0x1f4
54+
MX53_PAD_EIM_A18__GPIO2_20 0x1f4
55+
>;
56+
};
57+
};
58+
59+
&ldb {
60+
pinctrl-names = "default";
61+
pinctrl-0 = <&pinctrl_lvds0>;
62+
status = "okay";
63+
64+
lvds0: lvds-channel@0 {
65+
reg = <0>;
66+
fsl,data-mapping = "spwg";
67+
fsl,data-width = <24>;
68+
status = "okay";
69+
70+
port@2 {
71+
reg = <2>;
72+
73+
lvds0_out: endpoint {
74+
remote-endpoint = <&lvds_decoder_in>;
75+
};
76+
};
77+
};
78+
};
79+
80+
&panel_rgb_in {
81+
remote-endpoint = <&lvds_decoder_out>;
82+
};
83+
84+
&spi_ts {
85+
pinctrl-0 = <&pinctrl_spi_gpio>;
86+
pinctrl-names = "default";
87+
88+
sck-gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>;
89+
miso-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
90+
mosi-gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>;
91+
cs-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
92+
};
93+
94+
&touchscreen {
95+
interrupts-extended = <&gpio3 22 IRQ_TYPE_EDGE_BOTH>;
96+
pendown-gpio = <&gpio3 22 GPIO_ACTIVE_LOW>;
97+
};
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1+
// SPDX-License-Identifier: GPL-2.0+
2+
//
3+
// Copyright 2023 Linaro Ltd.
4+
5+
/dts-v1/;
6+
7+
#include <dt-bindings/pwm/pwm.h>
8+
#include "imx53-sk-imx53-atm0700d4.dtsi"
9+
10+
/ {
11+
display: disp0 {
12+
compatible = "fsl,imx-parallel-display";
13+
interface-pix-fmt = "rgb24";
14+
pinctrl-0 = <&pinctrl_rgb24>;
15+
pinctrl-names = "default";
16+
17+
#address-cells = <1>;
18+
#size-cells = <0>;
19+
20+
port@0 {
21+
reg = <0>;
22+
23+
display0_in: endpoint {
24+
remote-endpoint = <&ipu_di0_disp0>;
25+
};
26+
};
27+
28+
port@1 {
29+
reg = <1>;
30+
31+
display_out: endpoint {
32+
remote-endpoint = <&panel_rgb_in>;
33+
};
34+
};
35+
};
36+
37+
};
38+
39+
&iomuxc {
40+
pinctrl_rgb24: rgb24grp {
41+
fsl,pins = <
42+
MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5
43+
MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5
44+
MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5
45+
MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5
46+
MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5
47+
MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5
48+
MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5
49+
MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5
50+
MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5
51+
MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5
52+
MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5
53+
MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5
54+
MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5
55+
MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5
56+
MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5
57+
MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5
58+
MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5
59+
MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5
60+
MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5
61+
MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5
62+
MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5
63+
MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5
64+
MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5
65+
MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5
66+
MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5
67+
MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5
68+
MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5
69+
MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5
70+
>;
71+
};
72+
73+
pinctrl_spi_gpio: spigrp {
74+
fsl,pins = <
75+
MX53_PAD_SD1_DATA1__GPIO1_17 0x1f4
76+
MX53_PAD_GPIO_7__GPIO1_7 0x1f4
77+
MX53_PAD_PATA_DATA3__GPIO2_3 0x1f4
78+
MX53_PAD_PATA_DATA8__GPIO2_8 0x1f4
79+
>;
80+
};
81+
};
82+
83+
&ipu_di0_disp0 {
84+
remote-endpoint = <&display0_in>;
85+
};
86+
87+
&panel {
88+
enable-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
89+
};
90+
91+
&panel_rgb_in {
92+
remote-endpoint = <&display_out>;
93+
};
94+
95+
&pwm1 {
96+
status = "disabled";
97+
};
98+
99+
&spi_ts {
100+
pinctrl-0 = <&pinctrl_spi_gpio>;
101+
pinctrl-names = "default";
102+
103+
sck-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
104+
mosi-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
105+
miso-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
106+
cs-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
107+
};
108+
109+
&touchscreen {
110+
interrupts-extended = <&gpio2 6 IRQ_TYPE_EDGE_BOTH>;
111+
pendown-gpio = <&gpio2 6 GPIO_ACTIVE_LOW>;
112+
};
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1+
// SPDX-License-Identifier: GPL-2.0+
2+
//
3+
// Copyright 2023 Linaro Ltd.
4+
5+
/dts-v1/;
6+
7+
#include <dt-bindings/pwm/pwm.h>
8+
#include "imx53-sk-imx53.dts"
9+
10+
/ {
11+
panel: panel-rgb {
12+
compatible = "powertip,ph800480t013-idf02";
13+
14+
port {
15+
panel_rgb_in: endpoint {
16+
};
17+
};
18+
};
19+
20+
spi_ts: spi {
21+
compatible = "spi-gpio";
22+
#address-cells = <0x1>;
23+
#size-cells = <0x0>;
24+
25+
num-chipselects = <1>;
26+
27+
touchscreen: touchscreen@0 {
28+
reg = <0>;
29+
compatible = "ti,ads7843";
30+
spi-max-frequency = <300000>;
31+
32+
ti,vref-mv = /bits/ 16 <3300>;
33+
ti,x-plate-ohms = /bits/ 16 <450>;
34+
ti,y-plate-ohms = /bits/ 16 <250>;
35+
ti,debounce-tol = /bits/ 16 <10>;
36+
ti,debounce-rep = /bits/ 16 <0>;
37+
touchscreen-size-x = <4096>;
38+
touchscreen-size-y = <4096>;
39+
touchscreen-swapped-x-y;
40+
touchscreen-max-pressure = <100>;
41+
42+
wakeup-source;
43+
};
44+
};
45+
};

arch/arm/boot/dts/nxp/imx/imx53.dtsi

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -275,7 +275,7 @@
275275
ecspi1: spi@50010000 {
276276
#address-cells = <1>;
277277
#size-cells = <0>;
278-
compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
278+
compatible = "fsl,imx53-ecspi";
279279
reg = <0x50010000 0x4000>;
280280
interrupts = <36>;
281281
clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
@@ -701,7 +701,7 @@
701701
ecspi2: spi@63fac000 {
702702
#address-cells = <1>;
703703
#size-cells = <0>;
704-
compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
704+
compatible = "fsl,imx53-ecspi";
705705
reg = <0x63fac000 0x4000>;
706706
interrupts = <37>;
707707
clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,

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