Commit 2eb6836
dt-bindings: cache: sifive,ccache0: Add ESWIN EIC7700 SoC compatibility
This cache controller is also used on the ESWIN EIC7700 SoC.
However, it have 256KB private L2 Cache and shared L3 Cache of 4MB.
So add dedicated compatible string for it.
Signed-off-by: Pritesh Patel <pritesh.patel@einfochips.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>1 parent 0af2f6b commit 2eb6836
1 file changed
Lines changed: 41 additions & 3 deletions
Lines changed: 41 additions & 3 deletions
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