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willdeaconwilldeacon
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Merge branch 'for-next/rip-vpipt' into for-next/core
* for-next/rip-vpipt: arm64: Rename reserved values for CTR_EL0.L1Ip arm64: Kill detection of VPIPT i-cache policy KVM: arm64: Remove VPIPT I-cache handling
2 parents dd9168a + f35c32c commit 3043177

7 files changed

Lines changed: 4 additions & 95 deletions

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‎arch/arm64/include/asm/cache.h‎

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -58,7 +58,6 @@ static inline unsigned int arch_slab_minalign(void)
5858
#define CTR_L1IP(ctr) SYS_FIELD_GET(CTR_EL0, L1Ip, ctr)
5959

6060
#define ICACHEF_ALIASING 0
61-
#define ICACHEF_VPIPT 1
6261
extern unsigned long __icache_flags;
6362

6463
/*
@@ -70,11 +69,6 @@ static inline int icache_is_aliasing(void)
7069
return test_bit(ICACHEF_ALIASING, &__icache_flags);
7170
}
7271

73-
static __always_inline int icache_is_vpipt(void)
74-
{
75-
return test_bit(ICACHEF_VPIPT, &__icache_flags);
76-
}
77-
7872
static inline u32 cache_type_cwg(void)
7973
{
8074
return SYS_FIELD_GET(CTR_EL0, CWG, read_cpuid_cachetype());

‎arch/arm64/include/asm/kvm_mmu.h‎

Lines changed: 0 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -243,13 +243,6 @@ static inline size_t __invalidate_icache_max_range(void)
243243

244244
static inline void __invalidate_icache_guest_page(void *va, size_t size)
245245
{
246-
/*
247-
* VPIPT I-cache maintenance must be done from EL2. See comment in the
248-
* nVHE flavor of __kvm_tlb_flush_vmid_ipa().
249-
*/
250-
if (icache_is_vpipt() && read_sysreg(CurrentEL) != CurrentEL_EL2)
251-
return;
252-
253246
/*
254247
* Blow the whole I-cache if it is aliasing (i.e. VIPT) or the
255248
* invalidation range exceeds our arbitrary limit on invadations by

‎arch/arm64/kernel/cpuinfo.c‎

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -36,8 +36,6 @@ static struct cpuinfo_arm64 boot_cpu_data;
3636
static inline const char *icache_policy_str(int l1ip)
3737
{
3838
switch (l1ip) {
39-
case CTR_EL0_L1Ip_VPIPT:
40-
return "VPIPT";
4139
case CTR_EL0_L1Ip_VIPT:
4240
return "VIPT";
4341
case CTR_EL0_L1Ip_PIPT:
@@ -388,9 +386,6 @@ static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info)
388386
switch (l1ip) {
389387
case CTR_EL0_L1Ip_PIPT:
390388
break;
391-
case CTR_EL0_L1Ip_VPIPT:
392-
set_bit(ICACHEF_VPIPT, &__icache_flags);
393-
break;
394389
case CTR_EL0_L1Ip_VIPT:
395390
default:
396391
/* Assume aliasing */

‎arch/arm64/kvm/hyp/nvhe/pkvm.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@
1212
#include <nvhe/pkvm.h>
1313
#include <nvhe/trap_handler.h>
1414

15-
/* Used by icache_is_vpipt(). */
15+
/* Used by icache_is_aliasing(). */
1616
unsigned long __icache_flags;
1717

1818
/* Used by kvm_get_vttbr(). */

‎arch/arm64/kvm/hyp/nvhe/tlb.c‎

Lines changed: 0 additions & 61 deletions
Original file line numberDiff line numberDiff line change
@@ -105,28 +105,6 @@ void __kvm_tlb_flush_vmid_ipa(struct kvm_s2_mmu *mmu,
105105
dsb(ish);
106106
isb();
107107

108-
/*
109-
* If the host is running at EL1 and we have a VPIPT I-cache,
110-
* then we must perform I-cache maintenance at EL2 in order for
111-
* it to have an effect on the guest. Since the guest cannot hit
112-
* I-cache lines allocated with a different VMID, we don't need
113-
* to worry about junk out of guest reset (we nuke the I-cache on
114-
* VMID rollover), but we do need to be careful when remapping
115-
* executable pages for the same guest. This can happen when KSM
116-
* takes a CoW fault on an executable page, copies the page into
117-
* a page that was previously mapped in the guest and then needs
118-
* to invalidate the guest view of the I-cache for that page
119-
* from EL1. To solve this, we invalidate the entire I-cache when
120-
* unmapping a page from a guest if we have a VPIPT I-cache but
121-
* the host is running at EL1. As above, we could do better if
122-
* we had the VA.
123-
*
124-
* The moral of this story is: if you have a VPIPT I-cache, then
125-
* you should be running with VHE enabled.
126-
*/
127-
if (icache_is_vpipt())
128-
icache_inval_all_pou();
129-
130108
__tlb_switch_to_host(&cxt);
131109
}
132110

@@ -157,28 +135,6 @@ void __kvm_tlb_flush_vmid_ipa_nsh(struct kvm_s2_mmu *mmu,
157135
dsb(nsh);
158136
isb();
159137

160-
/*
161-
* If the host is running at EL1 and we have a VPIPT I-cache,
162-
* then we must perform I-cache maintenance at EL2 in order for
163-
* it to have an effect on the guest. Since the guest cannot hit
164-
* I-cache lines allocated with a different VMID, we don't need
165-
* to worry about junk out of guest reset (we nuke the I-cache on
166-
* VMID rollover), but we do need to be careful when remapping
167-
* executable pages for the same guest. This can happen when KSM
168-
* takes a CoW fault on an executable page, copies the page into
169-
* a page that was previously mapped in the guest and then needs
170-
* to invalidate the guest view of the I-cache for that page
171-
* from EL1. To solve this, we invalidate the entire I-cache when
172-
* unmapping a page from a guest if we have a VPIPT I-cache but
173-
* the host is running at EL1. As above, we could do better if
174-
* we had the VA.
175-
*
176-
* The moral of this story is: if you have a VPIPT I-cache, then
177-
* you should be running with VHE enabled.
178-
*/
179-
if (icache_is_vpipt())
180-
icache_inval_all_pou();
181-
182138
__tlb_switch_to_host(&cxt);
183139
}
184140

@@ -205,10 +161,6 @@ void __kvm_tlb_flush_vmid_range(struct kvm_s2_mmu *mmu,
205161
dsb(ish);
206162
isb();
207163

208-
/* See the comment in __kvm_tlb_flush_vmid_ipa() */
209-
if (icache_is_vpipt())
210-
icache_inval_all_pou();
211-
212164
__tlb_switch_to_host(&cxt);
213165
}
214166

@@ -246,18 +198,5 @@ void __kvm_flush_vm_context(void)
246198
/* Same remark as in __tlb_switch_to_guest() */
247199
dsb(ish);
248200
__tlbi(alle1is);
249-
250-
/*
251-
* VIPT and PIPT caches are not affected by VMID, so no maintenance
252-
* is necessary across a VMID rollover.
253-
*
254-
* VPIPT caches constrain lookup and maintenance to the active VMID,
255-
* so we need to invalidate lines with a stale VMID to avoid an ABA
256-
* race after multiple rollovers.
257-
*
258-
*/
259-
if (icache_is_vpipt())
260-
asm volatile("ic ialluis");
261-
262201
dsb(ish);
263202
}

‎arch/arm64/kvm/hyp/vhe/tlb.c‎

Lines changed: 0 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -216,18 +216,5 @@ void __kvm_flush_vm_context(void)
216216
{
217217
dsb(ishst);
218218
__tlbi(alle1is);
219-
220-
/*
221-
* VIPT and PIPT caches are not affected by VMID, so no maintenance
222-
* is necessary across a VMID rollover.
223-
*
224-
* VPIPT caches constrain lookup and maintenance to the active VMID,
225-
* so we need to invalidate lines with a stale VMID to avoid an ABA
226-
* race after multiple rollovers.
227-
*
228-
*/
229-
if (icache_is_vpipt())
230-
asm volatile("ic ialluis");
231-
232219
dsb(ish);
233220
}

‎arch/arm64/tools/sysreg‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2004,9 +2004,10 @@ Field 27:24 CWG
20042004
Field 23:20 ERG
20052005
Field 19:16 DminLine
20062006
Enum 15:14 L1Ip
2007-
0b00 VPIPT
2007+
# This was named as VPIPT in the ARM but now documented as reserved
2008+
0b00 RESERVED_VPIPT
20082009
# This is named as AIVIVT in the ARM but documented as reserved
2009-
0b01 RESERVED
2010+
0b01 RESERVED_AIVIVT
20102011
0b10 VIPT
20112012
0b11 PIPT
20122013
EndEnum

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