@@ -102,13 +102,13 @@ static int jpeg_v2_5_sw_init(void *handle)
102102
103103 /* JPEG DJPEG POISON EVENT */
104104 r = amdgpu_irq_add_id (adev , amdgpu_ih_clientid_jpeg [i ],
105- VCN_2_6__SRCID_DJPEG0_POISON , & adev -> jpeg .inst [i ].irq );
105+ VCN_2_6__SRCID_DJPEG0_POISON , & adev -> jpeg .inst [i ].ras_poison_irq );
106106 if (r )
107107 return r ;
108108
109109 /* JPEG EJPEG POISON EVENT */
110110 r = amdgpu_irq_add_id (adev , amdgpu_ih_clientid_jpeg [i ],
111- VCN_2_6__SRCID_EJPEG0_POISON , & adev -> jpeg .inst [i ].irq );
111+ VCN_2_6__SRCID_EJPEG0_POISON , & adev -> jpeg .inst [i ].ras_poison_irq );
112112 if (r )
113113 return r ;
114114 }
@@ -221,6 +221,9 @@ static int jpeg_v2_5_hw_fini(void *handle)
221221 if (adev -> jpeg .cur_state != AMD_PG_STATE_GATE &&
222222 RREG32_SOC15 (JPEG , i , mmUVD_JRBC_STATUS ))
223223 jpeg_v2_5_set_powergating_state (adev , AMD_PG_STATE_GATE );
224+
225+ if (amdgpu_ras_is_supported (adev , AMDGPU_RAS_BLOCK__JPEG ))
226+ amdgpu_irq_put (adev , & adev -> jpeg .inst [i ].ras_poison_irq , 0 );
224227 }
225228
226229 return 0 ;
@@ -569,6 +572,14 @@ static int jpeg_v2_5_set_interrupt_state(struct amdgpu_device *adev,
569572 return 0 ;
570573}
571574
575+ static int jpeg_v2_6_set_ras_interrupt_state (struct amdgpu_device * adev ,
576+ struct amdgpu_irq_src * source ,
577+ unsigned int type ,
578+ enum amdgpu_interrupt_state state )
579+ {
580+ return 0 ;
581+ }
582+
572583static int jpeg_v2_5_process_interrupt (struct amdgpu_device * adev ,
573584 struct amdgpu_irq_src * source ,
574585 struct amdgpu_iv_entry * entry )
@@ -593,10 +604,6 @@ static int jpeg_v2_5_process_interrupt(struct amdgpu_device *adev,
593604 case VCN_2_0__SRCID__JPEG_DECODE :
594605 amdgpu_fence_process (& adev -> jpeg .inst [ip_instance ].ring_dec );
595606 break ;
596- case VCN_2_6__SRCID_DJPEG0_POISON :
597- case VCN_2_6__SRCID_EJPEG0_POISON :
598- amdgpu_jpeg_process_poison_irq (adev , source , entry );
599- break ;
600607 default :
601608 DRM_ERROR ("Unhandled interrupt: %d %d\n" ,
602609 entry -> src_id , entry -> src_data [0 ]);
@@ -725,6 +732,11 @@ static const struct amdgpu_irq_src_funcs jpeg_v2_5_irq_funcs = {
725732 .process = jpeg_v2_5_process_interrupt ,
726733};
727734
735+ static const struct amdgpu_irq_src_funcs jpeg_v2_6_ras_irq_funcs = {
736+ .set = jpeg_v2_6_set_ras_interrupt_state ,
737+ .process = amdgpu_jpeg_process_poison_irq ,
738+ };
739+
728740static void jpeg_v2_5_set_irq_funcs (struct amdgpu_device * adev )
729741{
730742 int i ;
@@ -735,6 +747,9 @@ static void jpeg_v2_5_set_irq_funcs(struct amdgpu_device *adev)
735747
736748 adev -> jpeg .inst [i ].irq .num_types = 1 ;
737749 adev -> jpeg .inst [i ].irq .funcs = & jpeg_v2_5_irq_funcs ;
750+
751+ adev -> jpeg .inst [i ].ras_poison_irq .num_types = 1 ;
752+ adev -> jpeg .inst [i ].ras_poison_irq .funcs = & jpeg_v2_6_ras_irq_funcs ;
738753 }
739754}
740755
@@ -800,6 +815,7 @@ const struct amdgpu_ras_block_hw_ops jpeg_v2_6_ras_hw_ops = {
800815static struct amdgpu_jpeg_ras jpeg_v2_6_ras = {
801816 .ras_block = {
802817 .hw_ops = & jpeg_v2_6_ras_hw_ops ,
818+ .ras_late_init = amdgpu_jpeg_ras_late_init ,
803819 },
804820};
805821
0 commit comments