@@ -93,6 +93,7 @@ enum imx_mu_type {
9393struct imx_mu_dcfg {
9494 int (* tx )(struct imx_mu_priv * priv , struct imx_mu_con_priv * cp , void * data );
9595 int (* rx )(struct imx_mu_priv * priv , struct imx_mu_con_priv * cp );
96+ int (* rxdb )(struct imx_mu_priv * priv , struct imx_mu_con_priv * cp );
9697 void (* init )(struct imx_mu_priv * priv );
9798 enum imx_mu_type type ;
9899 u32 xTR ; /* Transmit Register0 */
@@ -179,6 +180,16 @@ static int imx_mu_generic_rx(struct imx_mu_priv *priv,
179180 return 0 ;
180181}
181182
183+ static int imx_mu_generic_rxdb (struct imx_mu_priv * priv ,
184+ struct imx_mu_con_priv * cp )
185+ {
186+ imx_mu_write (priv , IMX_MU_xSR_GIPn (priv -> dcfg -> type , cp -> idx ),
187+ priv -> dcfg -> xSR [IMX_MU_GSR ]);
188+ mbox_chan_received_data (cp -> chan , NULL );
189+
190+ return 0 ;
191+ }
192+
182193static int imx_mu_specific_tx (struct imx_mu_priv * priv , struct imx_mu_con_priv * cp , void * data )
183194{
184195 u32 * arg = data ;
@@ -329,9 +340,7 @@ static irqreturn_t imx_mu_isr(int irq, void *p)
329340 priv -> dcfg -> rx (priv , cp );
330341 } else if ((val == IMX_MU_xSR_GIPn (priv -> dcfg -> type , cp -> idx )) &&
331342 (cp -> type == IMX_MU_TYPE_RXDB )) {
332- imx_mu_write (priv , IMX_MU_xSR_GIPn (priv -> dcfg -> type , cp -> idx ),
333- priv -> dcfg -> xSR [IMX_MU_GSR ]);
334- mbox_chan_received_data (chan , NULL );
343+ priv -> dcfg -> rxdb (priv , cp );
335344 } else {
336345 dev_warn_ratelimited (priv -> dev , "Not handled interrupt\n" );
337346 return IRQ_NONE ;
@@ -639,6 +648,7 @@ static int imx_mu_remove(struct platform_device *pdev)
639648static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = {
640649 .tx = imx_mu_generic_tx ,
641650 .rx = imx_mu_generic_rx ,
651+ .rxdb = imx_mu_generic_rxdb ,
642652 .init = imx_mu_init_generic ,
643653 .xTR = 0x0 ,
644654 .xRR = 0x10 ,
@@ -649,6 +659,7 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = {
649659static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = {
650660 .tx = imx_mu_generic_tx ,
651661 .rx = imx_mu_generic_rx ,
662+ .rxdb = imx_mu_generic_rxdb ,
652663 .init = imx_mu_init_generic ,
653664 .xTR = 0x20 ,
654665 .xRR = 0x40 ,
@@ -659,7 +670,9 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = {
659670static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp = {
660671 .tx = imx_mu_generic_tx ,
661672 .rx = imx_mu_generic_rx ,
673+ .rxdb = imx_mu_generic_rxdb ,
662674 .init = imx_mu_init_generic ,
675+ .rxdb = imx_mu_generic_rxdb ,
663676 .type = IMX_MU_V2 ,
664677 .xTR = 0x200 ,
665678 .xRR = 0x280 ,
@@ -682,6 +695,7 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx8_scu = {
682695 .tx = imx_mu_specific_tx ,
683696 .rx = imx_mu_specific_rx ,
684697 .init = imx_mu_init_specific ,
698+ .rxdb = imx_mu_generic_rxdb ,
685699 .xTR = 0x0 ,
686700 .xRR = 0x10 ,
687701 .xSR = {0x20 , 0x20 , 0x20 , 0x20 },
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