Skip to content

Commit 318e431

Browse files
mukjoshialexdeucher
mukjoshi
authored and
alexdeucher
committed
drm/amdgpu: Enable IH retry CAM on GFX9
This patch enables the IH retry CAM on GFX9 series cards. This retry filter is used to prevent sending lots of retry interrupts in a short span of time and overflowing the IH ring buffer. This will also help reduce CPU interrupt workload. Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
1 parent e69c373 commit 318e431

7 files changed

Lines changed: 88 additions & 49 deletions

File tree

‎drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -98,6 +98,8 @@ struct amdgpu_irq {
9898
struct irq_domain *domain; /* GPU irq controller domain */
9999
unsigned virq[AMDGPU_MAX_IRQ_SRC_ID];
100100
uint32_t srbm_soft_reset;
101+
u32 retry_cam_doorbell_index;
102+
bool retry_cam_enabled;
101103
};
102104

103105
void amdgpu_irq_disable_all(struct amdgpu_device *adev);

‎drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c‎

Lines changed: 34 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -555,32 +555,49 @@ static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
555555
const char *mmhub_cid;
556556
const char *hub_name;
557557
u64 addr;
558+
uint32_t cam_index = 0;
559+
int ret;
558560

559561
addr = (u64)entry->src_data[0] << 12;
560562
addr |= ((u64)entry->src_data[1] & 0xf) << 44;
561563

562564
if (retry_fault) {
563-
/* Returning 1 here also prevents sending the IV to the KFD */
565+
if (adev->irq.retry_cam_enabled) {
566+
/* Delegate it to a different ring if the hardware hasn't
567+
* already done it.
568+
*/
569+
if (entry->ih == &adev->irq.ih) {
570+
amdgpu_irq_delegate(adev, entry, 8);
571+
return 1;
572+
}
573+
574+
cam_index = entry->src_data[2] & 0x3ff;
564575

565-
/* Process it onyl if it's the first fault for this address */
566-
if (entry->ih != &adev->irq.ih_soft &&
567-
amdgpu_gmc_filter_faults(adev, entry->ih, addr, entry->pasid,
576+
ret = amdgpu_vm_handle_fault(adev, entry->pasid, addr, write_fault);
577+
WDOORBELL32(adev->irq.retry_cam_doorbell_index, cam_index);
578+
if (ret)
579+
return 1;
580+
} else {
581+
/* Process it onyl if it's the first fault for this address */
582+
if (entry->ih != &adev->irq.ih_soft &&
583+
amdgpu_gmc_filter_faults(adev, entry->ih, addr, entry->pasid,
568584
entry->timestamp))
569-
return 1;
585+
return 1;
570586

571-
/* Delegate it to a different ring if the hardware hasn't
572-
* already done it.
573-
*/
574-
if (entry->ih == &adev->irq.ih) {
575-
amdgpu_irq_delegate(adev, entry, 8);
576-
return 1;
577-
}
587+
/* Delegate it to a different ring if the hardware hasn't
588+
* already done it.
589+
*/
590+
if (entry->ih == &adev->irq.ih) {
591+
amdgpu_irq_delegate(adev, entry, 8);
592+
return 1;
593+
}
578594

579-
/* Try to handle the recoverable page faults by filling page
580-
* tables
581-
*/
582-
if (amdgpu_vm_handle_fault(adev, entry->pasid, addr, write_fault))
583-
return 1;
595+
/* Try to handle the recoverable page faults by filling page
596+
* tables
597+
*/
598+
if (amdgpu_vm_handle_fault(adev, entry->pasid, addr, write_fault))
599+
return 1;
600+
}
584601
}
585602

586603
if (!printk_ratelimit())

‎drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -238,7 +238,7 @@ static void nbio_v7_4_ih_doorbell_range(struct amdgpu_device *adev,
238238

239239
if (use_doorbell) {
240240
ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index);
241-
ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 4);
241+
ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 8);
242242
} else
243243
ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0);
244244

‎drivers/gpu/drm/amd/amdgpu/vega20_ih.c‎

Lines changed: 25 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -38,6 +38,11 @@
3838
#define mmIH_CHICKEN_ALDEBARAN 0x18d
3939
#define mmIH_CHICKEN_ALDEBARAN_BASE_IDX 0
4040

41+
#define mmIH_RETRY_INT_CAM_CNTL_ALDEBARAN 0x00ea
42+
#define mmIH_RETRY_INT_CAM_CNTL_ALDEBARAN_BASE_IDX 0
43+
#define IH_RETRY_INT_CAM_CNTL_ALDEBARAN__ENABLE__SHIFT 0x10
44+
#define IH_RETRY_INT_CAM_CNTL_ALDEBARAN__ENABLE_MASK 0x00010000L
45+
4146
static void vega20_ih_set_interrupt_funcs(struct amdgpu_device *adev);
4247

4348
/**
@@ -251,36 +256,14 @@ static int vega20_ih_enable_ring(struct amdgpu_device *adev,
251256
return 0;
252257
}
253258

254-
/**
255-
* vega20_ih_reroute_ih - reroute VMC/UTCL2 ih to an ih ring
256-
*
257-
* @adev: amdgpu_device pointer
258-
*
259-
* Reroute VMC and UMC interrupts on primary ih ring to
260-
* ih ring 1 so they won't lose when bunches of page faults
261-
* interrupts overwhelms the interrupt handler(VEGA20)
262-
*/
263-
static void vega20_ih_reroute_ih(struct amdgpu_device *adev)
259+
static uint32_t vega20_setup_retry_doorbell(u32 doorbell_index)
264260
{
265-
uint32_t tmp;
261+
u32 val = 0;
266262

267-
/* vega20 ih reroute will go through psp this
268-
* function is used for newer asics starting arcturus
269-
*/
270-
if (adev->ip_versions[OSSSYS_HWIP][0] >= IP_VERSION(4, 2, 1)) {
271-
/* Reroute to IH ring 1 for VMC */
272-
WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x12);
273-
tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA);
274-
tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
275-
tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
276-
WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp);
277-
278-
/* Reroute IH ring 1 for UTCL2 */
279-
WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x1B);
280-
tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA);
281-
tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
282-
WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp);
283-
}
263+
val = REG_SET_FIELD(val, IH_DOORBELL_RPTR, OFFSET, doorbell_index);
264+
val = REG_SET_FIELD(val, IH_DOORBELL_RPTR, ENABLE, 1);
265+
266+
return val;
284267
}
285268

286269
/**
@@ -333,8 +316,6 @@ static int vega20_ih_irq_init(struct amdgpu_device *adev)
333316

334317
for (i = 0; i < ARRAY_SIZE(ih); i++) {
335318
if (ih[i]->ring_size) {
336-
if (i == 1)
337-
vega20_ih_reroute_ih(adev);
338319
ret = vega20_ih_enable_ring(adev, ih[i]);
339320
if (ret)
340321
return ret;
@@ -347,6 +328,20 @@ static int vega20_ih_irq_init(struct amdgpu_device *adev)
347328

348329
pci_set_master(adev->pdev);
349330

331+
/* Allocate the doorbell for IH Retry CAM */
332+
adev->irq.retry_cam_doorbell_index = (adev->doorbell_index.ih + 3) << 1;
333+
WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RETRY_CAM,
334+
vega20_setup_retry_doorbell(adev->irq.retry_cam_doorbell_index));
335+
336+
/* Enable IH Retry CAM */
337+
if (adev->ip_versions[OSSSYS_HWIP][0] == IP_VERSION(4, 4, 0))
338+
WREG32_FIELD15(OSSSYS, 0, IH_RETRY_INT_CAM_CNTL_ALDEBARAN,
339+
ENABLE, 1);
340+
else
341+
WREG32_FIELD15(OSSSYS, 0, IH_RETRY_INT_CAM_CNTL, ENABLE, 1);
342+
343+
adev->irq.retry_cam_enabled = true;
344+
350345
/* enable interrupts */
351346
ret = vega20_ih_toggle_interrupts(adev, true);
352347
if (ret)

‎drivers/gpu/drm/amd/amdkfd/kfd_svm.c‎

Lines changed: 9 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2172,7 +2172,15 @@ static void svm_range_drain_retry_fault(struct svm_range_list *svms)
21722172
pr_debug("drain retry fault gpu %d svms %p\n", i, svms);
21732173

21742174
amdgpu_ih_wait_on_checkpoint_process_ts(pdd->dev->adev,
2175-
&pdd->dev->adev->irq.ih1);
2175+
pdd->dev->adev->irq.retry_cam_enabled ?
2176+
&pdd->dev->adev->irq.ih :
2177+
&pdd->dev->adev->irq.ih1);
2178+
2179+
if (pdd->dev->adev->irq.retry_cam_enabled)
2180+
amdgpu_ih_wait_on_checkpoint_process_ts(pdd->dev->adev,
2181+
&pdd->dev->adev->irq.ih_soft);
2182+
2183+
21762184
pr_debug("drain retry fault gpu %d svms 0x%p done\n", i, svms);
21772185
}
21782186
if (atomic_cmpxchg(&svms->drain_pagefaults, drain, 0) != drain)

‎drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_2_0_offset.h‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -135,6 +135,8 @@
135135
#define mmIH_RB_WPTR_ADDR_LO_BASE_IDX 0
136136
#define mmIH_DOORBELL_RPTR 0x0087
137137
#define mmIH_DOORBELL_RPTR_BASE_IDX 0
138+
#define mmIH_DOORBELL_RETRY_CAM 0x0088
139+
#define mmIH_DOORBELL_RETRY_CAM_BASE_IDX 0
138140
#define mmIH_RB_CNTL_RING1 0x008c
139141
#define mmIH_RB_CNTL_RING1_BASE_IDX 0
140142
#define mmIH_RB_BASE_RING1 0x008d
@@ -159,6 +161,8 @@
159161
#define mmIH_RB_WPTR_RING2_BASE_IDX 0
160162
#define mmIH_DOORBELL_RPTR_RING2 0x009f
161163
#define mmIH_DOORBELL_RPTR_RING2_BASE_IDX 0
164+
#define mmIH_RETRY_CAM_ACK 0x00a4
165+
#define mmIH_RETRY_CAM_ACK_BASE_IDX 0
162166
#define mmIH_VERSION 0x00a5
163167
#define mmIH_VERSION_BASE_IDX 0
164168
#define mmIH_CNTL 0x00c0
@@ -235,6 +239,8 @@
235239
#define mmIH_MMHUB_ERROR_BASE_IDX 0
236240
#define mmIH_MEM_POWER_CTRL 0x00e8
237241
#define mmIH_MEM_POWER_CTRL_BASE_IDX 0
242+
#define mmIH_RETRY_INT_CAM_CNTL 0x00e9
243+
#define mmIH_RETRY_INT_CAM_CNTL_BASE_IDX 0
238244
#define mmIH_REGISTER_LAST_PART2 0x00ff
239245
#define mmIH_REGISTER_LAST_PART2_BASE_IDX 0
240246
#define mmSEM_CLK_CTRL 0x0100

‎drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_2_0_sh_mask.h‎

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -349,6 +349,17 @@
349349
#define IH_DOORBELL_RPTR_RING2__ENABLE__SHIFT 0x1c
350350
#define IH_DOORBELL_RPTR_RING2__OFFSET_MASK 0x03FFFFFFL
351351
#define IH_DOORBELL_RPTR_RING2__ENABLE_MASK 0x10000000L
352+
//IH_RETRY_INT_CAM_CNTL
353+
#define IH_RETRY_INT_CAM_CNTL__CAM_SIZE__SHIFT 0x0
354+
#define IH_RETRY_INT_CAM_CNTL__BACK_PRESSURE_SKID_VALUE__SHIFT 0x8
355+
#define IH_RETRY_INT_CAM_CNTL__ENABLE__SHIFT 0x10
356+
#define IH_RETRY_INT_CAM_CNTL__BACK_PRESSURE_ENABLE__SHIFT 0x11
357+
#define IH_RETRY_INT_CAM_CNTL__PER_VF_ENTRY_SIZE__SHIFT 0x14
358+
#define IH_RETRY_INT_CAM_CNTL__CAM_SIZE_MASK 0x0000001FL
359+
#define IH_RETRY_INT_CAM_CNTL__BACK_PRESSURE_SKID_VALUE_MASK 0x00003F00L
360+
#define IH_RETRY_INT_CAM_CNTL__ENABLE_MASK 0x00010000L
361+
#define IH_RETRY_INT_CAM_CNTL__BACK_PRESSURE_ENABLE_MASK 0x00020000L
362+
#define IH_RETRY_INT_CAM_CNTL__PER_VF_ENTRY_SIZE_MASK 0x00300000L
352363
//IH_VERSION
353364
#define IH_VERSION__MINVER__SHIFT 0x0
354365
#define IH_VERSION__MAJVER__SHIFT 0x8

0 commit comments

Comments
 (0)