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chleroympe
chleroy
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mpe
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powerpc/603: Switch r0 and r3 in TLB miss handlers
In preparation of next patch that will perform some additional calculations to replace comparison, switch the use of r0 and r3 as r0 has some limitations in some instructions like 'addi/subi'. Also remove outdated comments about the meaning of each register. The registers are used for many things and it would be difficult to accurately describe all things done with a given register. The function is now small enough to get a global view without much description. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://msgid.link/566af5e87685b1a85d3182549c0d520ce2d8877a.1724173828.git.christophe.leroy@csgroup.eu
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Lines changed: 38 additions & 56 deletions

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‎arch/powerpc/kernel/head_book3s_32.S‎

Lines changed: 38 additions & 56 deletions
Original file line numberDiff line numberDiff line change
@@ -411,47 +411,41 @@ END_FTR_SECTION_IFSET(CPU_FTR_FPU_UNAVAILABLE)
411411
*/
412412
. = INTERRUPT_INST_TLB_MISS_603
413413
InstructionTLBMiss:
414-
/*
415-
* r0: userspace flag (later scratch)
416-
* r1: linux style pte ( later becomes ppc hardware pte )
417-
* r2: ptr to linux-style pte
418-
* r3: fault address
419-
*/
420414
/* Get PTE (linux-style) and check access */
421-
mfspr r3,SPRN_IMISS
415+
mfspr r0,SPRN_IMISS
422416
#ifdef CONFIG_EXECMEM
423417
lis r1, TASK_SIZE@h /* check if kernel address */
424-
cmplw 0,r1,r3
418+
cmplw 0,r1,r0
425419
#endif
426420
mfspr r2, SPRN_SDR1
427421
li r1,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
428422
rlwinm r2, r2, 28, 0xfffff000
429423
#ifdef CONFIG_EXECMEM
430-
li r0, 3
424+
li r3, 3
431425
bgt- 112f
432426
lis r2, (swapper_pg_dir - PAGE_OFFSET)@ha /* if kernel address, use */
433-
li r0, 0
427+
li r3, 0
434428
addi r2, r2, (swapper_pg_dir - PAGE_OFFSET)@l /* kernel page table */
435429
#endif
436-
112: rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
430+
112: rlwimi r2,r0,12,20,29 /* insert top 10 bits of address */
437431
lwz r2,0(r2) /* get pmd entry */
438432
rlwinm. r2,r2,0,0,19 /* extract address of pte page */
439433
beq- InstructionAddressInvalid /* return if no mapping */
440-
rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
434+
rlwimi r2,r0,22,20,29 /* insert next 10 bits of address */
441435
lwz r2,0(r2) /* get linux-style pte */
442436
andc. r1,r1,r2 /* check access & ~permission */
443437
bne- InstructionAddressInvalid /* return if access not permitted */
444438
/* Convert linux-style PTE to low word of PPC-style PTE */
445439
#ifdef CONFIG_EXECMEM
446-
rlwimi r2, r0, 0, 31, 31 /* userspace ? -> PP lsb */
440+
rlwimi r2, r3, 0, 31, 31 /* userspace ? -> PP lsb */
447441
#endif
448442
ori r1, r1, 0xe06 /* clear out reserved bits */
449443
andc r1, r2, r1 /* PP = user? 1 : 0 */
450444
BEGIN_FTR_SECTION
451445
rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */
452446
END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
453447
mtspr SPRN_RPA,r1
454-
tlbli r3
448+
tlbli r0
455449
mfspr r3,SPRN_SRR1 /* Need to restore CR0 */
456450
mtcrf 0x80,r3
457451
rfi
@@ -480,35 +474,29 @@ InstructionAddressInvalid:
480474
*/
481475
. = INTERRUPT_DATA_LOAD_TLB_MISS_603
482476
DataLoadTLBMiss:
483-
/*
484-
* r0: userspace flag (later scratch)
485-
* r1: linux style pte ( later becomes ppc hardware pte )
486-
* r2: ptr to linux-style pte
487-
* r3: fault address
488-
*/
489477
/* Get PTE (linux-style) and check access */
490-
mfspr r3,SPRN_DMISS
478+
mfspr r0,SPRN_DMISS
491479
lis r1, TASK_SIZE@h /* check if kernel address */
492-
cmplw 0,r1,r3
480+
cmplw 0,r1,r0
493481
mfspr r2, SPRN_SDR1
494482
li r1, _PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_READ
495483
rlwinm r2, r2, 28, 0xfffff000
496-
li r0, 3
484+
li r3, 3
497485
bgt- 112f
498486
lis r2, (swapper_pg_dir - PAGE_OFFSET)@ha /* if kernel address, use */
499-
li r0, 0
487+
li r3, 0
500488
addi r2, r2, (swapper_pg_dir - PAGE_OFFSET)@l /* kernel page table */
501-
112: rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
489+
112: rlwimi r2,r0,12,20,29 /* insert top 10 bits of address */
502490
lwz r2,0(r2) /* get pmd entry */
503491
rlwinm. r2,r2,0,0,19 /* extract address of pte page */
504492
beq- DataAddressInvalid /* return if no mapping */
505-
rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
493+
rlwimi r2,r0,22,20,29 /* insert next 10 bits of address */
506494
lwz r2,0(r2) /* get linux-style pte */
507495
andc. r1,r1,r2 /* check access & ~permission */
508496
bne- DataAddressInvalid /* return if access not permitted */
509497
/* Convert linux-style PTE to low word of PPC-style PTE */
510498
rlwinm r1,r2,32-9,30,30 /* _PAGE_WRITE -> PP msb */
511-
rlwimi r2,r0,0,30,31 /* userspace ? -> PP */
499+
rlwimi r2,r3,0,30,31 /* userspace ? -> PP */
512500
rlwimi r1,r2,32-3,24,24 /* _PAGE_WRITE -> _PAGE_DIRTY */
513501
xori r1,r1,_PAGE_DIRTY /* clear dirty when not rw */
514502
ori r1,r1,0xe04 /* clear out reserved bits */
@@ -518,23 +506,23 @@ BEGIN_FTR_SECTION
518506
END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
519507
mtspr SPRN_RPA,r1
520508
BEGIN_MMU_FTR_SECTION
521-
li r0,1
509+
li r3,1
522510
mfspr r1,SPRN_SPRG_603_LRU
523-
rlwinm r2,r3,20,27,31 /* Get Address bits 15:19 */
524-
slw r0,r0,r2
525-
xor r1,r0,r1
526-
srw r0,r1,r2
511+
rlwinm r2,r0,20,27,31 /* Get Address bits 15:19 */
512+
slw r3,r3,r2
513+
xor r1,r3,r1
514+
srw r3,r1,r2
527515
mtspr SPRN_SPRG_603_LRU,r1
528516
mfspr r2,SPRN_SRR1
529-
rlwimi r2,r0,31-14,14,14
517+
rlwimi r2,r3,31-14,14,14
530518
mtspr SPRN_SRR1,r2
531519
mtcrf 0x80,r2
532-
tlbld r3
520+
tlbld r0
533521
rfi
534522
MMU_FTR_SECTION_ELSE
535523
mfspr r2,SPRN_SRR1 /* Need to restore CR0 */
536524
mtcrf 0x80,r2
537-
tlbld r3
525+
tlbld r0
538526
rfi
539527
ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_NEED_DTLB_SW_LRU)
540528
DataAddressInvalid:
@@ -560,34 +548,28 @@ DataAddressInvalid:
560548
*/
561549
. = INTERRUPT_DATA_STORE_TLB_MISS_603
562550
DataStoreTLBMiss:
563-
/*
564-
* r0: userspace flag (later scratch)
565-
* r1: linux style pte ( later becomes ppc hardware pte )
566-
* r2: ptr to linux-style pte
567-
* r3: fault address
568-
*/
569551
/* Get PTE (linux-style) and check access */
570-
mfspr r3,SPRN_DMISS
552+
mfspr r0,SPRN_DMISS
571553
lis r1, TASK_SIZE@h /* check if kernel address */
572-
cmplw 0,r1,r3
554+
cmplw 0,r1,r0
573555
mfspr r2, SPRN_SDR1
574556
li r1, _PAGE_RW | _PAGE_DIRTY | _PAGE_PRESENT | _PAGE_ACCESSED
575557
rlwinm r2, r2, 28, 0xfffff000
576-
li r0, 3
558+
li r3, 3
577559
bgt- 112f
578560
lis r2, (swapper_pg_dir - PAGE_OFFSET)@ha /* if kernel address, use */
579-
li r0, 0
561+
li r3, 0
580562
addi r2, r2, (swapper_pg_dir - PAGE_OFFSET)@l /* kernel page table */
581-
112: rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
563+
112: rlwimi r2,r0,12,20,29 /* insert top 10 bits of address */
582564
lwz r2,0(r2) /* get pmd entry */
583565
rlwinm. r2,r2,0,0,19 /* extract address of pte page */
584566
beq- DataAddressInvalid /* return if no mapping */
585-
rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
567+
rlwimi r2,r0,22,20,29 /* insert next 10 bits of address */
586568
lwz r2,0(r2) /* get linux-style pte */
587569
andc. r1,r1,r2 /* check access & ~permission */
588570
bne- DataAddressInvalid /* return if access not permitted */
589571
/* Convert linux-style PTE to low word of PPC-style PTE */
590-
rlwimi r2,r0,0,31,31 /* userspace ? -> PP lsb */
572+
rlwimi r2,r3,0,31,31 /* userspace ? -> PP lsb */
591573
li r1,0xe06 /* clear out reserved bits & PP msb */
592574
andc r1,r2,r1 /* PP = user? 1: 0 */
593575
BEGIN_FTR_SECTION
@@ -597,23 +579,23 @@ END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
597579
mfspr r2,SPRN_SRR1 /* Need to restore CR0 */
598580
mtcrf 0x80,r2
599581
BEGIN_MMU_FTR_SECTION
600-
li r0,1
582+
li r3,1
601583
mfspr r1,SPRN_SPRG_603_LRU
602-
rlwinm r2,r3,20,27,31 /* Get Address bits 15:19 */
603-
slw r0,r0,r2
604-
xor r1,r0,r1
605-
srw r0,r1,r2
584+
rlwinm r2,r0,20,27,31 /* Get Address bits 15:19 */
585+
slw r3,r3,r2
586+
xor r1,r3,r1
587+
srw r3,r1,r2
606588
mtspr SPRN_SPRG_603_LRU,r1
607589
mfspr r2,SPRN_SRR1
608-
rlwimi r2,r0,31-14,14,14
590+
rlwimi r2,r3,31-14,14,14
609591
mtspr SPRN_SRR1,r2
610592
mtcrf 0x80,r2
611-
tlbld r3
593+
tlbld r0
612594
rfi
613595
MMU_FTR_SECTION_ELSE
614596
mfspr r2,SPRN_SRR1 /* Need to restore CR0 */
615597
mtcrf 0x80,r2
616-
tlbld r3
598+
tlbld r0
617599
rfi
618600
ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_NEED_DTLB_SW_LRU)
619601

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