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dt-bindings: clock: qcom: document Kaanapali DISPCC clock controller
Document device tree bindings for display clock controller for Qualcomm Kaanapali SoC. Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260107-kaanapali-mmcc-v3-v3-4-8e10adc236a8@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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‎Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml‎

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domains on SM8550, SM8650, SM8750 and few other platforms.
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See also:
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- include/dt-bindings/clock/qcom,kaanapali-dispcc.h
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- include/dt-bindings/clock/qcom,sm8550-dispcc.h
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- include/dt-bindings/clock/qcom,sm8650-dispcc.h
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- include/dt-bindings/clock/qcom,sm8750-dispcc.h
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properties:
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compatible:
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enum:
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- qcom,kaanapali-dispcc
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- qcom,sar2130p-dispcc
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- qcom,sm8550-dispcc
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- qcom,sm8650-dispcc

‎include/dt-bindings/clock/qcom,kaanapali-dispcc.h‎

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_KAANAPALI_H
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#define _DT_BINDINGS_CLK_QCOM_DISP_CC_KAANAPALI_H
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/* DISP_CC clocks */
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#define DISP_CC_ESYNC0_CLK 0
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#define DISP_CC_ESYNC0_CLK_SRC 1
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#define DISP_CC_ESYNC1_CLK 2
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#define DISP_CC_ESYNC1_CLK_SRC 3
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#define DISP_CC_MDSS_ACCU_SHIFT_CLK 4
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#define DISP_CC_MDSS_AHB1_CLK 5
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#define DISP_CC_MDSS_AHB_CLK 6
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#define DISP_CC_MDSS_AHB_CLK_SRC 7
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#define DISP_CC_MDSS_AHB_SWI_CLK 8
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#define DISP_CC_MDSS_AHB_SWI_DIV_CLK_SRC 9
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#define DISP_CC_MDSS_BYTE0_CLK 10
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#define DISP_CC_MDSS_BYTE0_CLK_SRC 11
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#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 12
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#define DISP_CC_MDSS_BYTE0_INTF_CLK 13
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#define DISP_CC_MDSS_BYTE1_CLK 14
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#define DISP_CC_MDSS_BYTE1_CLK_SRC 15
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#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 16
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#define DISP_CC_MDSS_BYTE1_INTF_CLK 17
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#define DISP_CC_MDSS_DPTX0_AUX_CLK 18
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#define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 19
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#define DISP_CC_MDSS_DPTX0_CRYPTO_CLK 20
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#define DISP_CC_MDSS_DPTX0_LINK_CLK 21
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#define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 22
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#define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 23
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#define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 24
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#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK 25
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#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 26
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#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK 27
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#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 28
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#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 29
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#define DISP_CC_MDSS_DPTX1_AUX_CLK 30
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#define DISP_CC_MDSS_DPTX1_AUX_CLK_SRC 31
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#define DISP_CC_MDSS_DPTX1_CRYPTO_CLK 32
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#define DISP_CC_MDSS_DPTX1_LINK_CLK 33
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#define DISP_CC_MDSS_DPTX1_LINK_CLK_SRC 34
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#define DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC 35
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#define DISP_CC_MDSS_DPTX1_LINK_INTF_CLK 36
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#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK 37
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#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC 38
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#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK 39
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#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC 40
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#define DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK 41
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#define DISP_CC_MDSS_DPTX2_AUX_CLK 42
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#define DISP_CC_MDSS_DPTX2_AUX_CLK_SRC 43
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#define DISP_CC_MDSS_DPTX2_CRYPTO_CLK 44
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#define DISP_CC_MDSS_DPTX2_LINK_CLK 45
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#define DISP_CC_MDSS_DPTX2_LINK_CLK_SRC 46
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#define DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC 47
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#define DISP_CC_MDSS_DPTX2_LINK_INTF_CLK 48
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#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK 49
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#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC 50
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#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK 51
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#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC 52
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#define DISP_CC_MDSS_DPTX3_AUX_CLK 53
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#define DISP_CC_MDSS_DPTX3_AUX_CLK_SRC 54
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#define DISP_CC_MDSS_DPTX3_CRYPTO_CLK 55
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#define DISP_CC_MDSS_DPTX3_LINK_CLK 56
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#define DISP_CC_MDSS_DPTX3_LINK_CLK_SRC 57
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#define DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC 58
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#define DISP_CC_MDSS_DPTX3_LINK_INTF_CLK 59
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#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK 60
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#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC 61
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#define DISP_CC_MDSS_ESC0_CLK 62
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#define DISP_CC_MDSS_ESC0_CLK_SRC 63
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#define DISP_CC_MDSS_ESC1_CLK 64
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#define DISP_CC_MDSS_ESC1_CLK_SRC 65
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#define DISP_CC_MDSS_MDP1_CLK 66
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#define DISP_CC_MDSS_MDP_CLK 67
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#define DISP_CC_MDSS_MDP_CLK_SRC 68
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#define DISP_CC_MDSS_MDP_LUT1_CLK 69
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#define DISP_CC_MDSS_MDP_LUT_CLK 70
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#define DISP_CC_MDSS_MDP_SS_IP_CLK 71
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#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 72
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#define DISP_CC_MDSS_PCLK0_CLK 73
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#define DISP_CC_MDSS_PCLK0_CLK_SRC 74
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#define DISP_CC_MDSS_PCLK1_CLK 75
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#define DISP_CC_MDSS_PCLK1_CLK_SRC 76
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#define DISP_CC_MDSS_PCLK2_CLK 77
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#define DISP_CC_MDSS_PCLK2_CLK_SRC 78
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#define DISP_CC_MDSS_VSYNC1_CLK 79
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#define DISP_CC_MDSS_VSYNC_CLK 80
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#define DISP_CC_MDSS_VSYNC_CLK_SRC 81
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#define DISP_CC_OSC_CLK 82
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#define DISP_CC_OSC_CLK_SRC 83
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#define DISP_CC_PLL0 84
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#define DISP_CC_PLL1 85
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#define DISP_CC_PLL2 86
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#define DISP_CC_SLEEP_CLK 87
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#define DISP_CC_XO_CLK 88
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/* DISP_CC power domains */
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#define DISP_CC_MDSS_CORE_GDSC 0
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#define DISP_CC_MDSS_CORE_INT2_GDSC 1
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/* DISP_CC resets */
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#define DISP_CC_MDSS_CORE_BCR 0
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#define DISP_CC_MDSS_CORE_INT2_BCR 1
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#define DISP_CC_MDSS_RSCC_BCR 2
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#endif

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