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airliedairlied
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Merge tag 'drm-msm-next-2021-06-23b' of https://gitlab.freedesktop.org/drm/msm into drm-next
* devcoredump support for display errors * dpu: irq cleanup/refactor * dpu: dt bindings conversion to yaml * dsi: dt bindings conversion to yaml * mdp5: alpha/blend_mode/zpos support * a6xx: cached coherent buffer support * a660 support * gpu iova fault improvements: - info about which block triggered the fault, etc - generation of gpu devcoredump on fault * assortment of other cleanups and fixes Signed-off-by: Dave Airlie <airlied@redhat.com> From: Rob Clark <robdclark@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/CAF6AEGs4=qsGBBbyn-4JWqW4-YUSTKh67X3DsPQ=T2D9aXKqNA@mail.gmail.com
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‎Documentation/devicetree/bindings/display/msm/dp-controller.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MSM Display Port Controller
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maintainers:
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- Kuogee Hsieh <khsieh@codeaurora.org>
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description: |
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Device tree bindings for DisplayPort host controller for MSM targets
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that are compatible with VESA DisplayPort interface specification.
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properties:
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compatible:
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enum:
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- qcom,sc7180-dp
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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items:
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- description: AHB clock to enable register access
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- description: Display Port AUX clock
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- description: Display Port Link clock
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- description: Link interface clock between DP and PHY
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- description: Display Port Pixel clock
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clock-names:
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items:
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- const: core_iface
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- const: core_aux
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- const: ctrl_link
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- const: ctrl_link_iface
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- const: stream_pixel
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assigned-clocks:
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items:
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- description: link clock source
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- description: pixel clock source
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assigned-clock-parents:
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items:
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- description: phy 0 parent
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- description: phy 1 parent
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phys:
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maxItems: 1
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phy-names:
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items:
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- const: dp
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operating-points-v2:
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maxItems: 1
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power-domains:
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maxItems: 1
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"#sound-dai-cells":
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const: 0
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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properties:
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port@0:
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$ref: /schemas/graph.yaml#/properties/port
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description: Input endpoint of the controller
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port@1:
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$ref: /schemas/graph.yaml#/properties/port
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description: Output endpoint of the controller
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- phys
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- phy-names
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- "#sound-dai-cells"
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- power-domains
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- ports
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,dispcc-sc7180.h>
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#include <dt-bindings/power/qcom-aoss-qmp.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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displayport-controller@ae90000 {
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compatible = "qcom,sc7180-dp";
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reg = <0xae90000 0x1400>;
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interrupt-parent = <&mdss>;
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interrupts = <12>;
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clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
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<&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
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<&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
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<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
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clock-names = "core_iface", "core_aux",
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"ctrl_link",
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"ctrl_link_iface", "stream_pixel";
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assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
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<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
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assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
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phys = <&dp_phy>;
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phy-names = "dp";
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#sound-dai-cells = <0>;
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power-domains = <&rpmhpd SC7180_CX>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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endpoint {
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remote-endpoint = <&dpu_intf0_out>;
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};
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};
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port@1 {
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reg = <1>;
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endpoint {
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remote-endpoint = <&typec>;
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};
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};
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};
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};
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...

‎Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml‎

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# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/msm/dpu-sc7180.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Display DPU dt properties for SC7180 target
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maintainers:
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- Krishna Manikandan <mkrishn@codeaurora.org>
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description: |
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Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
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sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
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bindings of MDSS and DPU are mentioned for SC7180 target.
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properties:
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compatible:
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items:
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- const: qcom,sc7180-mdss
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reg:
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maxItems: 1
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reg-names:
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const: mdss
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power-domains:
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maxItems: 1
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clocks:
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items:
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- description: Display AHB clock from gcc
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- description: Display AHB clock from dispcc
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- description: Display core clock
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clock-names:
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items:
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- const: iface
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- const: ahb
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- const: core
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interrupts:
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maxItems: 1
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interrupt-controller: true
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"#address-cells": true
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"#size-cells": true
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"#interrupt-cells":
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const: 1
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iommus:
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items:
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- description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
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ranges: true
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interconnects:
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items:
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- description: Interconnect path specifying the port ids for data bus
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interconnect-names:
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const: mdp0-mem
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patternProperties:
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"^display-controller@[0-9a-f]+$":
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type: object
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description: Node containing the properties of DPU.
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properties:
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compatible:
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items:
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- const: qcom,sc7180-dpu
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reg:
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items:
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- description: Address offset and size for mdp register set
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- description: Address offset and size for vbif register set
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reg-names:
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items:
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- const: mdp
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- const: vbif
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clocks:
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items:
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- description: Display hf axi clock
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- description: Display ahb clock
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- description: Display rotator clock
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- description: Display lut clock
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- description: Display core clock
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- description: Display vsync clock
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clock-names:
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items:
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- const: bus
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- const: iface
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- const: rot
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- const: lut
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- const: core
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- const: vsync
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interrupts:
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maxItems: 1
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power-domains:
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maxItems: 1
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operating-points-v2: true
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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description: |
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Contains the list of output ports from DPU device. These ports
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connect to interfaces that are external to the DPU hardware,
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such as DSI, DP etc. Each output port contains an endpoint that
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describes how it is connected to an external interface.
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properties:
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port@0:
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$ref: /schemas/graph.yaml#/properties/port
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description: DPU_INTF1 (DSI1)
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port@2:
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$ref: /schemas/graph.yaml#/properties/port
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description: DPU_INTF0 (DP)
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required:
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- port@0
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required:
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- compatible
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- reg
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- reg-names
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- clocks
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- interrupts
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- power-domains
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- operating-points-v2
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- ports
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required:
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- compatible
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- reg
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- reg-names
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- power-domains
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- clocks
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- interrupts
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- interrupt-controller
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- iommus
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- ranges
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,dispcc-sc7180.h>
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#include <dt-bindings/clock/qcom,gcc-sc7180.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interconnect/qcom,sdm845.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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display-subsystem@ae00000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "qcom,sc7180-mdss";
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reg = <0xae00000 0x1000>;
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reg-names = "mdss";
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power-domains = <&dispcc MDSS_GDSC>;
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clocks = <&gcc GCC_DISP_AHB_CLK>,
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<&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_CLK>;
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clock-names = "iface", "ahb", "core";
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interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>;
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interconnect-names = "mdp0-mem";
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iommus = <&apps_smmu 0x800 0x2>;
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ranges;
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display-controller@ae01000 {
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compatible = "qcom,sc7180-dpu";
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reg = <0x0ae01000 0x8f000>,
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<0x0aeb0000 0x2008>;
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reg-names = "mdp", "vbif";
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clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
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<&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&dispcc DISP_CC_MDSS_ROT_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_CLK>,
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<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
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clock-names = "bus", "iface", "rot", "lut", "core",
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"vsync";
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interrupt-parent = <&mdss>;
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interrupts = <0>;
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power-domains = <&rpmhpd SC7180_CX>;
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operating-points-v2 = <&mdp_opp_table>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dpu_intf1_out: endpoint {
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remote-endpoint = <&dsi0_in>;
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};
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};
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port@2 {
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reg = <2>;
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dpu_intf0_out: endpoint {
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remote-endpoint = <&dp_in>;
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};
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};
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};
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};
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};
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...

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