drm/amdgpu: fix mmhub register base coding error

Yang Wang · alexdeucher · commit 347fafe0eb46 · 2022-12-06T10:18:18.000-05:00
fix MMHUB register base coding error. Fixes: ec68375 ("drm/amdgpu/gmc10: program the smallK fragment size") Signed-off-by: Yang Wang <KevinYang.Wang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
@@ -319,7 +319,7 @@ static void mmhub_v2_0_init_cache_regs(struct amdgpu_device *adev)
 
 	tmp = mmMMVM_L2_CNTL5_DEFAULT;
 	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
-	WREG32_SOC15(GC, 0, mmMMVM_L2_CNTL5, tmp);
+	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL5, tmp);
 }
 
 static void mmhub_v2_0_enable_system_domain(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
@@ -243,7 +243,7 @@ static void mmhub_v2_3_init_cache_regs(struct amdgpu_device *adev)
 
 	tmp = mmMMVM_L2_CNTL5_DEFAULT;
 	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
-	WREG32_SOC15(GC, 0, mmMMVM_L2_CNTL5, tmp);
+	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL5, tmp);
 }
 
 static void mmhub_v2_3_enable_system_domain(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c
@@ -275,7 +275,7 @@ static void mmhub_v3_0_init_cache_regs(struct amdgpu_device *adev)
 
 	tmp = regMMVM_L2_CNTL5_DEFAULT;
 	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
-	WREG32_SOC15(GC, 0, regMMVM_L2_CNTL5, tmp);
+	WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL5, tmp);
 }
 
 static void mmhub_v3_0_enable_system_domain(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c
@@ -269,7 +269,7 @@ static void mmhub_v3_0_1_init_cache_regs(struct amdgpu_device *adev)
 
 	tmp = regMMVM_L2_CNTL5_DEFAULT;
 	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
-	WREG32_SOC15(GC, 0, regMMVM_L2_CNTL5, tmp);
+	WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL5, tmp);
 }
 
 static void mmhub_v3_0_1_enable_system_domain(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c
@@ -268,7 +268,7 @@ static void mmhub_v3_0_2_init_cache_regs(struct amdgpu_device *adev)
 
 	tmp = regMMVM_L2_CNTL5_DEFAULT;
 	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
-	WREG32_SOC15(GC, 0, regMMVM_L2_CNTL5, tmp);
+	WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL5, tmp);
 }
 
 static void mmhub_v3_0_2_enable_system_domain(struct amdgpu_device *adev)

Original file line number	Diff line number	Diff line change
`@@ -319,7 +319,7 @@ static void mmhub_v2_0_init_cache_regs(struct amdgpu_device *adev)`
`319`	`319`
`320`	`320`	`tmp = mmMMVM_L2_CNTL5_DEFAULT;`
`321`	`321`	`tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);`
`322`		`- WREG32_SOC15(GC, 0, mmMMVM_L2_CNTL5, tmp);`
	`322`	`+ WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL5, tmp);`
`323`	`323`	`}`
`324`	`324`
`325`	`325`	`static void mmhub_v2_0_enable_system_domain(struct amdgpu_device *adev)`
Original file line number	Diff line number	Diff line change
`@@ -243,7 +243,7 @@ static void mmhub_v2_3_init_cache_regs(struct amdgpu_device *adev)`
`243`	`243`
`244`	`244`	`tmp = mmMMVM_L2_CNTL5_DEFAULT;`
`245`	`245`	`tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);`
`246`		`- WREG32_SOC15(GC, 0, mmMMVM_L2_CNTL5, tmp);`
	`246`	`+ WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL5, tmp);`
`247`	`247`	`}`
`248`	`248`
`249`	`249`	`static void mmhub_v2_3_enable_system_domain(struct amdgpu_device *adev)`
Original file line number	Diff line number	Diff line change
`@@ -275,7 +275,7 @@ static void mmhub_v3_0_init_cache_regs(struct amdgpu_device *adev)`
`275`	`275`
`276`	`276`	`tmp = regMMVM_L2_CNTL5_DEFAULT;`
`277`	`277`	`tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);`
`278`		`- WREG32_SOC15(GC, 0, regMMVM_L2_CNTL5, tmp);`
	`278`	`+ WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL5, tmp);`
`279`	`279`	`}`
`280`	`280`
`281`	`281`	`static void mmhub_v3_0_enable_system_domain(struct amdgpu_device *adev)`
Original file line number	Diff line number	Diff line change
`@@ -269,7 +269,7 @@ static void mmhub_v3_0_1_init_cache_regs(struct amdgpu_device *adev)`
`269`	`269`
`270`	`270`	`tmp = regMMVM_L2_CNTL5_DEFAULT;`
`271`	`271`	`tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);`
`272`		`- WREG32_SOC15(GC, 0, regMMVM_L2_CNTL5, tmp);`
	`272`	`+ WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL5, tmp);`
`273`	`273`	`}`
`274`	`274`
`275`	`275`	`static void mmhub_v3_0_1_enable_system_domain(struct amdgpu_device *adev)`
Original file line number	Diff line number	Diff line change
`@@ -268,7 +268,7 @@ static void mmhub_v3_0_2_init_cache_regs(struct amdgpu_device *adev)`
`268`	`268`
`269`	`269`	`tmp = regMMVM_L2_CNTL5_DEFAULT;`
`270`	`270`	`tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);`
`271`		`- WREG32_SOC15(GC, 0, regMMVM_L2_CNTL5, tmp);`
	`271`	`+ WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL5, tmp);`
`272`	`272`	`}`
`273`	`273`
`274`	`274`	`static void mmhub_v3_0_2_enable_system_domain(struct amdgpu_device *adev)`